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Bind key to change Path end type(ex:extend,truncate,round,variable)

 Hi all, Can anyone please help me on this, How to set the bindkey for changing path end type from extend to truncate or round or variable in IC615 Virtuoso Layout Suite. Thanks in advance....

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increase virtual memory to sn_compile.sh

 How do I increase the virtual memory allocated to sn_compile.sh? We have an environment compilation crashing because of an “out of virtual memory” error. 

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problem with IGBT model from advanls Lib

Hello, I am tying to use the AA pspice to tune the IGBT parameters.I am using orcad 16.3.When adding the IGBT component from the "advanls" library, a simulation error occurd! Although the IGBT is...

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OCEAN SCRIPT for getting dynamic energy consumption

Hi everyone,I designed a circuit through cadence virtuoso and extracted the spice netlist (.scs) from the ADE. Then I want to do circuit simulation many many times with different input variables by...

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A problem in ELC (Encounter Library Characterizer)

Hi, I am characterizing standard cells, but I have the following problem. When I run db_spice, elc says "[WARNING(db_spice)]No spice simulation to do, please check the cell/process list for any error",...

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Built-in Power Calculation

Hi,I am trying to find out how Cadence calculates the "pwr" operating point parameter of a MOS transistor, and it is almost imposible to get that information.In a previous forum, it was mentioned that...

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RVE CN command equivalent to PVS

 Hi, Were currently swithing from using Calibre RVE to PVS.Do someone of you know the equivalent value of the "CN" in the .db file of RVE into PVS?, by the way the CN means Cell name wich basically...

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No Pspice tempelate of misclinear.olb

 Hello!, I am desiging a divider circuit using the AD534 on pspice. I found the component part in the misclinear.olb but I get a warning that there is no pspice template for this part "U1". I knew that...

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After editing the schematic part, the symbols are not get updated in board?

I had placed the component, then for the routing convenient the part pin has been swapped in schematic. After the swapping of pins i had updated the net list option. In that what option should i gave...

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How to use the some set of vias under the top to bottom layers?

Hi.. For the specific board design the top and bottom layers should been get connected set of arrays.For that option i had tried to use the thieving parameters. In that rectangle type shape has enabled...

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Using Skill to create a Padstack with a Thermal subclass that has geometry...

Hi all, Trying to pick up Skill here on my own and I'm having a bit of difficulty trying to get a specific part of my code to work. I am writing a Skill program that will be able to automatically...

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Insufficient memory to continue{MMSIM12}.

Dear All,I was running a pexed circuit with APS enabled ( Manual, Cores-4). CPU has 4 cores.In spectre.out, I saw the simulation (both DC & Transient) ended with ZERO errors proerley.But,...

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Short violation

 I did a verifyGeometry right after placeDesign -prePlaceOpt and had 1000 short violations.The messages are : SHORT: Special Wire of Net VSS & Pin of Cell U7178  ( M1 )Bounds : ( 277.600, 31.035 )...

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Unable to find the AD539 model

Hello! I want to use the AD539 in my circuit but I cannot find it. When I searched for it in the internet I found that it is in the Advanced Analysis Library List. So, I followed the steps on how to...

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Knowing associated TECH-FILE location

 Dear All,I have installed a main stream PDK in my Cadence enviornment.While creating a new library, I associated the techfile corresponding to this  PDK.Is there any way to know the location of the...

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Processing cadence result data from psf folder

 Dear All, There is a Spectre & MATLAB interface for plotting psf data. But this somehow not working in my case with latest MATALB2014. So I use Ocean Script for saving simulation data in text file...

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how could i use the "libInit.il" to add my own user-defined funtions when...

I've already finished a pcell with skill language within which i've called some my own user-defined functions from some other docments.So i load it like "load("xxx.il" in the CIW. OK! I've got my first...

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Library Conversion form layout to editor is possible?

Hi.. I had maintained some of the power modules in layout 9.2 version. But when i am try to use it for the editor is possible. Any import option is possible from .llb to .dra conversion. No i am using...

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VerilogA compiler

 Dear all,I'm using VerilogA model in my design in Cadence, I have some variables in the model that should be changed with time, actually I have two questions:1- Is there a way to display the value of...

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DRC & Create Netlist Error(ORCAP-36041): Duplicate Pin Name. Please renumber...

Hi,I have created many parts in OrCAD which have 'NC' pins - or other pins with similar names: IO,.. - when I run DRC or create netlist I see below error messages in the DRC report file or session...

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