I did a verifyGeometry right after placeDesign -prePlaceOpt and had 1000 short violations.
The messages are : SHORT:
Special Wire of Net VSS & Pin of Cell U7178 ( M1 )
Bounds : ( 277.600, 31.035 ) ( 280.600, 31.365 )
SHORT: Special Via of Net VDD & Pin of Cell U35043 ( M1 )
Bounds : ( 348.000, 14.835 ) ( 351.000, 15.165 )
The display showed the short aligned with the power stripes; I did the previous short violation's suggestion to ensure VDD, VSS are properly set. The standard cell is provided by foundry so it should be fine. Is there anything else I missed?