LibManager Edit Trigger/Callback
Hi, In the Virtuoso Library Manager when a cellview is double-clicked, it automatically opens for edit. However, I would like some things to happen just before a cell view is opened for edit (make a...
View ArticleResults Browser in IC5.10.41
Hi,I am using IC5.10.41 and wanted to know how can the below mentioned things be done.1. Is there a way to print the numerous output expression values for a simulation that was previously done? Till...
View Articlevirtuoso possible outputs in IC610
Hi,needed some help in using cadence IC610. Is there an provision in the Analog design environment or else where in virtuoso which directly gives the below values- power consumption capacitance area...
View ArticleCreating Smith Chart via Skill
Hi,I'm trying to plot S11 data on a Smith Chart using Skill. I've tried the following sequence:openResults("/path/to/psf/directory")selectResults("sp")wid=awvCreatePlotWindow()...
View ArticleOrcad capture and Orcad PCB Editor - Connectivity check
Is there a way I can highlight the reference designator or net (ref des) in Orcad capture and it is highlighted on Orcad PCB editor. I am having hard time finding the components from schematic and...
View ArticleTransient simulation - save state
Hi,I am a research scholar at IIT bombay, India. I have a long transient simulation running, which has frozen at 1.8us in a 10 us simulation. Is there any way to extract the state of the circuit and...
View ArticleProblem with scripts that require file browsers
Does anyone know of a workaround that would allow a script or axlShell() commands to select and populate afile browser if it pops up? It seems that the file browser form isn't recgonized. So...
View Article[Help] Tech file from cadence.
I am trying to export cadence layout to GDSII files and then import it to HFSS. When I import the files to HFSS, I get a flat sheets. It seems that I have to generate (or export) some sort of Tech file...
View ArticleProblem Photodiode modelling in Verilog-A
Hello everyone, So basically I'm working on my final year project where I have to Design a Camera. The front end of the circuitry is a photodiode. Because the foundries don't provide models, I had to...
View ArticleTop grid problem facing when trying to put the Routing on single side board?
Hi... I had a simple doubt in the grid placement,that is when i am try to put the single side board the top side routing should not be enabled., for that i had tried to remove the girds on the top...
View ArticleFootrprint Pin movement in not get moved to certain distance in the(.brd)??
Hi.. i had placed the components on the board for the single side routing. But when i am trying to move the 2 pin from the component the pin is not get moved. So i had tried the other option that, open...
View Articlehow to add BB Via in internal layer ??
Hi everyone,how to add buried via in inner layer even though i assigned the pad stack assigned for following producure. (set up--->assign BB via)
View ArticleOpening a text file in Allegro
Hi,Is there a way to open a text file in Allegro? Or if possible is there a way to place the text file in the "Show Element" window to make it active (hyperlink)? Here's my situation, I have a skill...
View ArticleMonte Carlo Analysis of I/Q amplitude and phase mismatch
Hi all, I am designing a divider circuit for I/Q components. I want to find phase and amplitude mismatch between I and Q components using Cadence with "Monte Carlo Analysis". Please let me know how to...
View ArticleAbstract Generator : Memory instance ABSTRACT&LEF views Generation.
Hello,I have sucessfully generated the ABSTRACT & LEF views for a standard-cell with the Abstract generator Tool, now I am trying to do the same for a memory instance which contains many cells...
View Articlehow to findout the permission of a library.
Hi..Is there a skill code that I can use to find out the permission of a library instead of clicking on the property button on a library to find out??Example: When I use the GUI from the lib browser, I...
View ArticleLabels are created in VLE while doing streaming in a GDS file.
Dear All,I streamed in a GDS file into a new library. While opening the top-level cell of the library in the layout editor (VLE) , I find a lot of text labels ( like I1,I2...I1667) are created in...
View ArticleZoom-in and Zoom-out graphics issues in Virtuso Layout Editor (...
Dear All,I am facing issues with Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151) in my machine.My layout is having a lot of transistors ( like SRAM or DAC) in a small area.While doing...
View ArticleModeling and simulation of FinFET in cadence
Hello. I m MTech student. I want to simulate FinFET based digital circuits. But I don't have a FinFET model in cadence. Please help me by providing an equivalent model of FinFET or any other way to...
View ArticleHow to run ADEXL without re-netlisting?
Hi, I am using ICFB 6.1.5-64b.Due to design-specific reasons, I want to include a blackboxed block into my testbench by hacking the netlist. It works fine in ADE because I can "include" the netlist in...
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