Abstract Generator : Memory instance ABSTRACT&LEF views Generation.

Hello,

I have sucessfully generated the ABSTRACT & LEF views for a standard-cell with the Abstract generator Tool, now I am trying to do the same for a memory instance which contains many cells (master control, array of bitcells, io ...). 

I have as input file : the layout of the memory instance, with all the input/ouput pins at the edges of the memory instances. Actually, the other intergrated blocks will communicate through these edged pins.

As far as now, the memory instance, contains all the cells (no flattened).

When I do the "Abstract Generation : Pin step" with Abstract Generator, I have the following messages, the step ends.

WARNING   (ABS-1502): Couldn't open master "cmosXXX_XXX_memMacros, top_blXXX_lresref, layout", referenced in cellview "cmosXXX_XXX_memTemplates_XXX, Inst_cellName, abstract.pin"

WARNING   (ABS-1502): Couldn't open master "cmosXXX_XXX_memMacros, array_blXXX_wlXXX_lresref, layout", referenced in cellview "cmosXXX_XXX_memTemplates_XXX, Inst_cellName, abstract.pin"

...

LOG       (ABS-1422): Running Pins 100 percent complete...

LOG       (ABS-1301): Cell Inst_cellName: Step Pins finished

1

REPLAY    (ABS-1429): 15  absSetCellProp("Inst_cellName" "symmetry" "None")

WARNING   (ABS-325): Cell Inst_cellName: Failed to set the property because the cell is either invalid or does not contain any of the valid views.Abstract Generator can set properties only on valid views, such as Pins,Extract,Abstract, that it has created.

---------

Message:

Couldn't open master libName, cellName, viewName, referenced in cellview libName, cellName, viewName.

absSkillMode()

absSkillMode()

absSetLibrary("cmosXXX_XXX_memTemplates_XXX")

absAttachTechLib("cmosXXX_tech")

absSetLibrary("cmosXXX_XXX_memTemplates_XXX")

absSelectCellFrom("Inst_cellName" "Inst_cellName")

absDisableUpdate()

absSetBinOption("Core" "PinsPowerNames" "vdd1 vdd2 vd3 vdd4 vdd5")

absSetBinOption("Core" "PinsGroundNames" "vss")

absSetBinOption("Core" "PinsOutputNames" "q")

absSetBinOption("Core" "PinsClockNames" "clk")

absSetBinOption("Core" "ExcludeExistingTerminals" "")

absSetBinOption("Core" "PinsBoundaryCreate" "off")

absEnableUpdate()

absPins()

absDisableUpdate()

absSetBinOption("Core" "ExtractSig" "false")

absSetBinOption("Core" "ExtractMustJoinAlways" "true")

absSetBinOption("Core" "ExtractPwr" "false")

absSetBinOption("Core" "ExtractMustJoinAlwaysPwr" "true")

absSetBinOption("Core" "ExtractAntennaGate" "(PO (PO and (DCO or PP or NP or VTH_P or VTH_N or VTL_P or VTL_N or OD ))) ")

absSetBinOption("Core" "ExtractUseNetInfo" "true")

absEnableUpdate()

absExtract()

absDisableUpdate()

absEnableUpdate()

absAbstract()

absSetOption("ExportLEFFile" "cmosXXX_XXX_memTemplates_XXX.lef")

absExportLEF()

absExit()

xxx/bin/abstract -replay xxx/cmosXXX_XXX_memTemplates/abstract.record -log abstract_batch.log -nogui

 

 

 

 

Thanks a lot !

 

P. 

 

PS : tool version : cadence_amsams2010.2c_mmsim &  IC6.1.5-64b.500.9