Dear All,
I am facing issues with Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151) in my machine.
My layout is having a lot of transistors ( like SRAM or DAC) in a small area.
While
doing zooming-in or zooming-out of the layout ( i.e. EDIT in place EIP
) of the cell, it becomes slow ( 2 to 3 seconds) for the layout-window
to settle to the actual final stage.
This is becoming very painful and irritating while doing the complex layout.
Can anybody please tell why this is happening. How it canbe made faster.
Kind Regards,