write a dynamic skill Gui
Hi, I was wondering if its possible ( and if it is then how exactly) can I write a gui in skill,that its fields ( stringFeild) are not pre defined as we normally do, but depends on (say) the number of...
View Articleprob signals from inside a block with Spectre
Hi All, Im attaching a short include file to my netlist: ITF0 (set_up_tf\<0\> hold_tf\<0\> setup_min_tf\<0\> hold_min_tf\<0\> I7.XI35\MM44:G vcca \I7.XI35\MM54:G vcca)...
View ArticleError with Spice Model ATF34143
HiI downloaded a Spice model from Avago Technologies http://www.avagotech.com/pages/en/rf_microwave/transistors/fet/atf-34143/ but the spice model seems to be not usable.The error message given...
View ArticlePrint Routed board in PCB Editor
After generating the gerber file in OrCAD Layout, I used the tool to check the GerBTool Archiving and print. How can I check the Archiving and print the PCB Editor 16.5. What tool can I use?
View Articlegroup routing_ from schem_16.6
is thr any way wherein we can initiate the group routing on PCB by selecting the group of pins on theschematic. Cross probing is working fine. I tried being in etch mode in PCB and then select the...
View ArticleError of vsource type=bit. "Waveform type must be specified ..."
Hi Mr. Beckett,Following your advice, I tried the bit vsource to generate a bit flow. However, an error came up.Here is my simulation circuit.
View Articleamsspice: *Error: terminated with error code 127
I'm trying to run a RAK, Introduction to AMS Designer SimulationI always get the following error:irun: *E,SPCERR: The program encountered one or more errors while processing the input SPICE file(s) in...
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do stb analysis on five stage invter ring osc
hi,everyone i designed a five stage ring osc,and each stage is made up of an inverter. I perform DC analysis first,and I found output voltage of each stage is at the half of VDD. Then I do...
View ArticleFlash Symbols/Thermal Relief
All,After Allegro offered positive planes,I think most of us w moved away from flash symbols and thermal vias. Having said that, is there a need to maintain a library of flash symbols. I have been...
View ArticleAnnotation fails on homogeneous parts
Hello,On Allegro Entry CIS, I have a design with homogeneous parts inside. These parts are named U?A, U?B.When I run an incremental annotation, the first part in the sheet is numbered (U1A and U1B) the...
View ArticleHow to creat pins of MOS transistor with fingers in pcell.
Hello. I have created MOS transistor pcell using ROD. But I have detected drawback. When number of fingers more than one, router doesn't connect drains or sources and in VXL I must connect pin of other...
View ArticleKeep power nets separate in a hiearchical design
Hello,Say that I instantiate the same block four times in a schematic, I’m using the SUBDESING_SUFFIX attribute to keep the same location value in each instance, for example, R1 becomes R1CH1 in...
View ArticleHow do I prevent a DRC Net shorting error in PCB design?
Good Morning,I have a devide that has 4 pins going to the same net, but 1 of those pins is a sense line that goes to another pin on an edge connector... All of the pins are connected together in the...
View ArticleProblem when running simulation with Verilog-AMS and SystemVerilog together...
Hi, I am now working on a AMS verification using irun. I have an analog module (Verilog-AMS model, .vams) and a logic module (SystemVerilog RTL netlist, .sv) and want to integrate them together for...
View Articledvi models
Hai , I need to simulate a dvi transmitter does any one has the model for a DVI transmitter if any one have the model (any) please help me regards agxin mj
View ArticlePIN SWAP OPTION IN CONCEPT HDL
Hi ,How can enable the pin swap option in concept hdl?Thanks,Karthik.
View ArticleDiff pair *uncoupled length* while routing at an angle of 45 degrees
Hi! I noticed that when I route my differential pair at an angle of 45 degrees then in Constraint manager the value of *uncoupled length* is increasing. Does it mean that the spacing is different while...
View ArticleUnable to map design without a suitable latch. [MAP-3] [synthesize]
The same design can be synthesized by Synopsys (syn-2010.03-SP3). No error happens. When I use Cadence RTL compiler, one error happens. The error information is listed as below. Library:...
View Articlefreeze with virtuoso layout
Hello, While using virtuoso layout (IC 6.15) , I got some freeze and virtuoso run infinitly. The HW ressource are not undersized, the issue seems to come from virtuoso.To go further I run strace unix...
View ArticleError Message Displayed when I give path of dsn file
Hi all I have created a design by defining new parts in the library and I have included these parts in my schematic. However, when I give the path of the DSN file the following error message gets...
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