rcp vs ple
what is difference between rcp and ple synthesis.how many types optimization techniques it does?what is meaning of rcp netlist ?Any one help me out above my queryThanksChiranjeeevi.Pandamaneni
View ArticlePutting track problems on the corner of the chamfering?????
Hi..I had routed the sample board and then when i am trying to slide the track means that time the corner of the tracks is been cutout. i don't what is the problem for that?I had attached the png image...
View ArticleNC-Verilog simulation error
I am new in using ncvlogI have an error when i am trying to simulate simple inverter |ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit...
View ArticleHow to put the copper area for the several nets in the PCB?
Hi I am concentrating on the BLDC motor drives, with three phase supply. After putting the tracks the specific area on the drive board is been get heating, so we have to provide that copper area....
View ArticleModify ADE Toolbar buttons
Hi,Is it possible to modify the ADE toolbars in virtuoso 6.1 ?There is a directory located at 06.15.511/share/cdssetup/dfII/toolbars/byApplication" which gives the templates for the toolbars for all of...
View ArticleCopy and Rename of a Pin in Symbol
Hi,Can someone help me with the skill commands to copy and rename a pin.Problem Def: I need to add a new pin in all my symbols. The symbol view can have different pin shapes (round, square, hexagon etc...
View Articleskill ruby interface for openaccess
Hi,I am asking for the best method to approach this problem. I would like to execute skill commands on a Cadence database in a unix shell command line. Ideally i would not want to worry if the ICFB...
View ArticleXL Layout issue with custom Library layout sourcing the Schematic.
I have a custom inverter layout that I built and my problem that I have is that when I do an update the on my layout the update takes my cutom layout cells and replaces them in pmos and nmos...
View ArticleHow to enable & disable legends on the pcb board?
Hi.. I created the drive board and then it had been get to be finishing stage. Before that we have align the top and bottom side legends. For that i had used the color dialog option and then i had...
View ArticleError while importing .gds in cadence IC 6.16
Hi, I get the follwing error while importing a .gds file in cadence IC 6.16 ERROR (XSTRM-80046): You are trying to modify the tech database, but the tech database is not writable. Check the tech...
View ArticleProgress bar for uncompress the package
Hi, I want to show a progress bar for uncompressing a package with skill code. And I find the progress bar function --hiDisplayProgressBox, but I have no idea about how to connect the uncompressing...
View Articlehow to add BB Via in internal layer ??
Hi everyone,how to add buried via in inner layer even though i assigned the pad stack assigned for following producure. (set up--->assign BB via)
View ArticleNet name
Hello Everyone, How to give net name on pcb editor,i am make pcb using pcb editor,am not would like to use capture or hdl model to make pcb,when i make pcb without these unable...
View ArticleHow to let the messages not show in shell terminal when use ipcBeginProcess ?
Hello All,I use ipcBeginProcess to do something , but I don't want the messages show in xterm , How to do it ? Thank you,Charley
View ArticleVoid on adjacent layer
Hi,On RF circuits need to create void on adjacent Plane layers below the RF cline run.Is there a skill,which can create void on adjacent layer/s when a cline is selected. Pls share if any. Thanks....
View ArticleNot finding a solution (academic member)
Hello. I am an academic member.I know that there is a Cadence solution for printing out/ transversing a circuit hierarchy, with SKILL, from my commerical career. The solution is a SKILL script, with...
View ArticleUltra librarian- .dra file, .psm file
Hi all, I am using OrCAD Capture CIS Lite and PCB Editor Lite. I am trying to design a simple circuit. But I'm not able to get the footprint of components. I downloaded the .bxl file from TI website...
View Articlepipo.log and strmOut.log
Hi,I am using IC 6.16. Is pipo.log the same as strmOut.log in IC 6.16?
View ArticleHow to multiply the result of a TABLE
I'm trying to model a magnetic circuit using a gyrator-capacitor approach. My magnetic paths are nonlinear, so I am using a nonideal transformer consisting of a VCVS and a CCCS with a turns ratio equal...
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