Hi All,
Im attaching a short include file to my netlist:
ITF0 (set_up_tf\<0\> hold_tf\<0\> setup_min_tf\<0\> hold_min_tf\<0\> I7.XI35\MM44:G vcca \
I7.XI35\MM54:G vcca) su_hd_vmon scale_to_units=1e-9 clk_n_factor=0.5 \
data_n_factor=0.5 min_max_measure_start_t=20n data_edge=0 \
clk_edge=1
ITF0 is a verilogA block that get 4 inputs and has for output ( 4 wires bus). Two of the inputs are vcca, and the other two are : I7.XI35\MM44:G & I7.XI35\MM54:G , which are names of nets from inside a DSPF. I can even see these signals in the results browser or calculator or ADE-XL( I do save these signals in advance). The thing is that all outputs of the verilogA are dead (the 4 wire bus).
When I place the same unit ( actual symbol ) on the same TB, in the same run ( running stimultanslly) with wires connected ( by name ) to the extracted block pins( in this case I7 which sit in top level)
I do get the all signals. I also verified that the inputs signals are identical between these two cases
It look like the connections of the inputs to the verilogA cell are not define right. In Pre layout it works fine.
This way ( below) it works fine, but in this method I don’t really probe the real location on net that I need, since in RC extraction the net is segmented into different segments because of the series resistors.
I6 (set_up\<0\> hold\<0\> setup_min\<0\> hold_min\<0\> clk_int vcca d_net2 \
vcca) su_hd_vmon scale_to_units=1e-9 clk_n_factor=0.5 \
data_n_factor=0.5 min_max_measure_start_t=20n data_edge=0 \
clk_edge=1
I would need you advise here ..