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Reading signals directly from transient analysis using "psf" command with data in SST2 format

April 2, 2013, 7:52 am
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 Hi,

I usually write out signals out of the transient analysis data using the "psf" command built into spectre. This is faster than using ocnPrint and simpler. 

I suddenly see the following error now:

"./psf/tran.tran.trn":1,2: Error 35, syntax error found, header table missing

Is anyone familiar with this? I have been using MMSIM 10.11.235 which works well for me for a while and have been able to write out waves using this command so far. The Spectre command line in my log file looks like this:

/cte/tools/cds/MMSIM/10.11.235/tools.lnx86/spectre/bin/64bit/spectre  \
        input.scs +escchars +log ../psf/spectre.out -format sst2 -raw  \
        ../psf ++aps +mt=8 +lqtimeout 900 -maxw 5 -maxn 5

 I don't see anything different from the usual scenario, although I am not sure whether I was using the +sst2 option in the past or +psfbin. I suspect that "psf" does not work in this case. 

 Would anyone know what utility I would need to use to get hold of the data now?

Thanks,

Vivek

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Cadence taking time for initialization

January 31, 2014, 10:46 am
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Dear Team,

I am running cadence in Ubuntu 12.04 32bit. While initialising/invoking any cadence GUI, it is taking relatively too much time(>10-20 sec). When it is running .cxt extention, it is taking time. Can you please tell me how can i solve this problem? Please find attached CDS log for your reference.

 Regards,

Darshak

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How to vertical how horizen mirror a pad in Allegro package symbol? How to clean design cache?

January 31, 2014, 8:53 am
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I did make a pad, however, I still want get it mirror horizen or vertical. The mirror function seems doesnot work with pad ( it only work when you mirror pin name)

So my question is how to mirror horizen or vertical of this pad?

And other quesiton is how to clean design cache? 

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IC6 Add Connectivity to Manually Routed Nets

January 29, 2014, 2:19 pm
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Hi guys,

I am using IC6.1.5.  We are editing the layout with the Layout Suite XL.  Many of the nets in the layout were manually routed and do not have connectivity.  How can I add connectivity to these nets?  Is there a tool that does this or perhaps a SKILL script?  Our connectivity problems are mostly on internal, unpinned nets.

In a specific layout, we are using Join Named Nets to get LVS clean.  This means that there is an open net (vgnd) in the layout and each segment has a pin placed on it to join the nets of this node to get LVS clean.  There are flashing markers in the layout that say "Warning: Illegal weak-connect connection on net vgnd"  How do we get rid of these markers?  If we add connectivity to the vgnd net, will the marker warning be removed?  Does IC6 understand the Join Named Nets concept?  

Thank you,

 Stephanie

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Cadence schematic access permission issues with mounted folders

January 31, 2014, 7:30 pm
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 Hi,

We recently moved from a 'Samba' based remote file mounting to  "sshfs" based file mounting . After the migration, we are unable to open any schematic in the mounted folders with write permission.

Upon trying to open the files we get an error

('SCH-1217') : Could not open'schamtic' for edit.

(DB-270000)  dBOpenCellViewByType: Unable to lock  database file for  'filepath'

Would you like to open it for read?

 The native linux permissions of the mounted folders look good and we are able to read/write files into the mounted folders from the command prompt. Any clues on why virtuoso thinks the mounted folders as 'read only' when linux permissions are good??

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alias or funckey

January 31, 2014, 9:20 pm
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I'd like to assign a key to toggle betwreen general/etch/placement with alias or funckey.

Is it possible to have a key toggle something like that?

 

 

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How to run Virtuoso on Linux Cluster

January 31, 2014, 9:27 pm
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 Hi there,

I've setup 3 node Linux Beowulf Cluster in order to run Cadence Virtuoso Circuit Simulation simultaneously on 3 cluster compute nodes. Whenever, I run Virtuoso, it opens three different instances of Virtuoso interface intead of distributing three different threads across three compute nodes?

Am I missing something or Virtuoso does not support multithread architecture?

Any help would be highly appreciated.

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Autorouting Using OrCAD 16.6 Demo Version

January 31, 2014, 9:53 pm
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 I have the demo version of OrCAD 16.6 and I'm currently reading "Complete PCB Design Using OrCAD Capture and PCB Editor" by Kraig Mitzner. I'm stuck halfway through chapter two on the part on autorouting. There doesn't appear to be an autoroute option, or I just can't find it. This book has been great so far, but what am I missing?

 

Thanks,

Mike 

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copy between designs?

January 31, 2014, 9:35 pm
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I have a line/frame I'd like to use around each board where I have versions numbers and notes listed. Right now I export as a DXF and then reimport to other design. It's painful.

Is there a better way to do what's basically just copy and paste?

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How to check and verify negative artwork?

February 1, 2014, 4:27 pm
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Dear all, how to import and verify negative plane layer artwork?

After generating the negative plane layer and important it to Allegro again, I can not see the copper of the negative plane layer, I only can see a negative image, even though I set the Xsecion of this layer to be negative.

How to do to be able to see the copper of the negative plane layer?  I want to see the copper , the same as I saw in .brd file.  Or is there a better way to check the negative plane layer artwork?

Thank you very much!

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Procedural interface for Virtuoso schematic navigator

February 1, 2014, 4:29 pm
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I am trying to get the hierarchical list of instances that a net is connected to. I found two flows and both have issues:

 

  1. Schematic Navigator --> Select Net --> Right-Mouse-click on the net in navigator --> Probe --> Add net and connected instance
    • This works great and it probes all the instances the net is connected to.
    • However the geGetAllProbe() returns the probeId of the net. I can't get the dbId of instances connected to the net procedurally. Is there a better way to get these instance dbIds?
  2. auProbeAddDevsForNet()
    • This auLvs() functionality is broken. Works on certain schematics but fails on many.
    • I also tried setting the graphic env variable probeNetDisplayCheckInstance and this did not work
    • windowId~>probeNetDisplayCheckInstance = t did not work either
    • Is this function supported at all?

 

I heard probing has been enhanced in IC616 and I am yet to try this.

Any help or insight into this is greatly appreicated.

-- PSoorya 

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Complex filter : Image Reject Ratio (IRR) calculation

February 4, 2014, 4:16 am
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Hi ,

How do I simulate IRR of complex filter.  ? ( A transient simulation of an IQ mixer followed by a complex filter and then look at dft of the output waveforms is one way ) 

Is there a cadence documentation for the same ?

 

Thanks,

Regards,

Vishal

 

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How to parallel or to increase the speed of simulation launching with ocean (distributed)

January 31, 2014, 1:52 am
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Hi,

I wrote an ocean script which has to do lot of simultations. It is working perfectly well but I would like to increase its speed. Currently I use run( ?jobName jobname ?queue lsf_queue ?mail nil ) to launch the simulations, and the following environnement variables:

envSetVal("asimenv.distributed" "removeJobData" 'boolean t)

envSetVal("asimenv.distributed" "showMessages" 'boolean nil) 

The simulation launching time is about 7s/sim (everything is lauched sequentially) and ocean returns:

Delete psf data in /path/blablabla/HSPICE/schematic/distributed/7703/psf.

submitting job... 

Does anybody know a way to decrease this launching time or to launch several simulation in the same time?

Thanks.

 

Thomas 

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SOI MOSFET Simulation with PSPICE?

February 17, 2012, 1:16 am
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Hi, Is it possible to simulate SOI MOSFETs with Orcad PSPICE using Berkeley`s BSIM SOI Model Cards?? Thanks
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Radial/polar placement !

September 4, 2013, 11:46 pm
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Hi all,

I have a circular board and the placement need to be arranged symmetrically. In PADs we have radial move that allows us to adjust radius/angle of the circular grid that snap components.

'Polar' command seems not feasible to place more than 1 component at one time.

Can you please suggest me some idea ?

Thanks, 

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Incremental update to Allegro

February 4, 2014, 8:01 am
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 Hello,

 I have been working on a PCB design in Allegro based on a Cadence schematic. I have removed a few components from the schematic during the PCB design and so need to update the schematic part annotations (to be incremental). This causes problems in Allegro when I create the new netlist. Is there a way of syncing the annotations between Cadence and Allegro? 

 Many thanks,

Matt

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triggering the done procedure for enterPoints()

September 12, 2013, 1:43 pm
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I am using an enterPoints function that does not seem to recognize use of the Enter key, or a double click (typical done trigger for enterPath) as triggers for its done procedure.  How does one trigger the done procedure for enterPoints?  The esc key is recognized as a cancel function.  The form contains a cancel button, but no done button.
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How to remove that Triangle on the pad

February 4, 2014, 10:33 am
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Hi, Have a easy question.

I did a symbol footprint, and at the central of that symbol, there is a pad. If I delete the pad number and place the pad, there will show a triangle in the middle of that pad.How to get rid of that triangle? And also will this unname pad triggers a DRC error in pcb layout?

Thanks 

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AMS simulation using ADE. How to save internal verilog module signals.

February 4, 2014, 11:56 am
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I am running an AMS simulation using ADE and am having troubling saving some of the signals in my verilog module. I created and imported a .csv file with the list of outputs I wanted to save. However, only some of the nets are saved. All of the saved nets were wires. None of my registers were saved. And not all of the wires were saved. I'm not sure how to fix this. Can anyone help me out. Thanks.
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Orcad Capture

February 4, 2014, 2:02 pm
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 When adding a "Place Net Alias" How do you add a line over the Net name?

You can do it when you make a symbol. But i can find it for the schematic end

 

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