Hi,
I am new to the reuse design concept.
Is it possible to use the 4 layer stackup reuse module(*.mdd) in 8 layer stackup or 10 layer stackup board without chaning the reuse module stackup?
Thank you
Hi,
I am new to the reuse design concept.
Is it possible to use the 4 layer stackup reuse module(*.mdd) in 8 layer stackup or 10 layer stackup board without chaning the reuse module stackup?
Thank you
Hi eveyone,
i have some doubt for Leading and Trailing Zeros.instead of leading Zero if i choose trailing zero what will happen.what is the use of Gerber RS274x why should i choose that format .if i choose another what will happen ??
what is the use of CONTINUE WITH UNDEFINED APERTURE is it default settings
H,
I am new to SKILL.
Please bear with my negligence.
I am trying to run the GUI example from this forum.(oferExample.il).
I opened the command prompt and gave cnskill -i -nongraph.
the cnskill window popped up.
load "oferExample.il"
It loaded it successfully.
Then i called the function oferExample().
It gives an error "undefined function: hiCreateStringField
Please tell what i am missing or if am doing it wrong.
Thanks
Anusha
Hello, i am both newbie in this forum and OrCAD. I need to simulate the circuit as shown below but i have a problem in Pspice:
INFO(ORPROBE-3183): Simulation running...
** Profile: "SCHEMATIC1-Full-Bridge" [ D:\Electrical & Electronics\Power Electronics\Simulation & Schematics\Orcad\full-bridge-pspi
Reading and checking circuit
ERROR(ORPSIM-16276): Can't find library
Circuit has errors ... run aborted
See output file for details
INFO(ORPROBE-3188): Simulation aborted
I am using UC3825 but it also says as follows:
WARNING(ORNET-1018): Connection to unmodeled pin U8 pin 'RT'
WARNING(ORNET-1018): Connection to unmodeled pin U8 pin 'CT'
Schematic: http://oi62.tinypic.com/qrdjzo.jpg
Hi,
I have looked at some previous posts and wanted to do the same, but
when I tried to execute,
$ldd Cadence/IC615/tools/dfII/bin/Xndx
I get a message,
ldd: Cadence/IC615/tools/dfII/bin/Xndx: No such file or directory
Is there any chance that this might be the reason for ADE XL to not run?
Or could anyone please point to reasons why it is not running?
Thanks,
Navi
Hi,
I'm trying to create custom sheet (border) starting from the US_8ths library provided by IC6.1.6.
The custom sheet, when instanced, should be pick up: library name, schematic name, creator's name, time created, modifier's name, time modified....
Do you have any example or document on this topic?
Your help is very appreciated.
Thanks.
Regards,
Coi
Hi guys,
I am using IC6.1.5. We are editing the layout with the Layout Suite XL. Many of the nets in the layout were manually routed and do not have connectivity. How can I add connectivity to these nets? Is there a tool that does this or perhaps a SKILL script? Our connectivity problems are mostly on internal, unpinned nets.
In a specific layout, we are using Join Named Nets to get LVS clean. This means that there is an open net (vgnd) in the layout and each segment has a pin placed on it to join the nets of this node to get LVS clean. There are flashing markers in the layout that say "Warning: Illegal weak-connect connection on net vgnd" How do we get rid of these markers? If we add connectivity to the vgnd net, will the marker warning be removed? Does IC6 understand the Join Named Nets concept?
Thank you,
Stephanie
Hi,
I have a power gated domain that I'm trying to implement that I'm having trouble with CTS.
I have 2 power domains : base_domain(always on) and gated_domain(power-gated).
Both domains have multiple clocks in the domains that I'm trying to synthesize clock tree for.
For some reason, when I perform ClockDesign, Encounter places the clock tree cells that belong in the gated_domain in the
base_domain. I tried setting -honorFence true in setCTSMode but it doesn't seem to help. The clock tree starts from the
gated_domain and crosses over to the base_domain. Is there a way to restrict the placement of clock tree
within its power domain? I cannot have the clock cells cross over from the gated_domain to the base_domain.
Hi,
I am using 16.6 and can easily slide vias, clines, etc. but not components. Sure it might cause some issues but if it a simple 2 pin component or even a DFN/QFN component with hug only turned on it wont screw everything up. Am I missing something or is this just not possible?
Thanks,
Aric
I am trying to redefine bind keys and menu items for some functions within the schematic editor as well as add another pulldown menu to the banner menu. I have working code that does this if I start the schemtic editor first by hand, and it works well. When I open up an additional schematic window, the bind keys and menu callback function overrides are all there, but the new pulldown menu is gone. I don't want to have to run the initialization script by hand everytime I open a new shematic window.
The code to re-assign the callback functions and new pulldown menu don't work unless a schematic window is opened first. I therfore open up a dummy schematic window, run my setup, and then close the dummy schematic window. I think this is kind of a kludge, and it doesn't keep my pulldown menu anyway. I also don't want to modify the menu files. Is there anyway to run a skill script every time a schematic editor starts up? I am running the IC615 version. Below is the initialization code snippet that I am using. I load this and run it within the .cdsinit in my home directory.
svID=deNewCellView("sandbox" "temp1" "schematic" "schematic" nil)
sv1ID=geGetWindowCellView(svID)
adCreateLayoutMenuItem = hiCreateMenuItem(?name 'adCreateLayoutMenuItem ?itemText "Create Layout" ?callback "adCreateLayout")
hiCreateMenu( 'adToolsPulldown "Tools" list( adCreateLayoutMenuItem ) )
hiInsertBannerMenu( hiGetCurrentWindow() 'adToolsPulldown 5 )
hiSetBindKey("Schematics" "None<Key>i" "adHiCreateInst( )")
hiSetBindKey("Schematics" "None<Key>w" "adHiCreateWire( )")
hiSetBindKey("Schematics" "None<Key>p" "adHiCreatePin( )")
hiSetMenuItemCallback(schAddMenu 'InstItem "adHiCreateInst()")
hiSetMenuItemCallback(schAddMenu 'WireItem "adHiCreateWire()")
hiSetMenuItemCallback(schAddMenu 'PinItem "adHiCreatePin()")
dbClose(sv1ID)
I did connect global power nets to all pins. Then did sroute. Then added the standard cells. And the geometry check gives me this errors, thousands of them:
Blockage of Cell U_BUF2/URAM/ram_reg[413][12]
bbox = (322.540, 1477.810) (322.600, 1478.170)
I am attaching picture pointing to the error with arrow. The blue lines you see are M1 VDD! and GND! lines, and I have checked the standard cell layout and confirmed that those power lines correctly overlap the power lines of standard cells.
I am not quite getting why the error checker is not happy and what kind of blockage of cell is it talking about? Whst exactly is blocked?
Hi all,
I am trying to use a variable for the value of a association list, but I get the variable name instead of the actual value.
Is there a way to use a variable fo the value?:
coupon_x=0 coupon_y=0
path='( ("xy_1" (coupon_x+80:coupon_y+0)) ("xy_2" (coupon_x+80:coupon_y-9)) ("xy_3" (coupon_x+68:coupon_y-21)) ("w" 30))
(("xy_1"
((coupon_x + 80):(coupon_y + 0))
)
("xy_2"
((coupon_x + 80):(coupon_y - 9))
)
("xy_3"
((coupon_x + 68):(coupon_y - 21))
)
("w" 30)
)
My system: IC6.1.5
In stb analysis, based on the bode plots I am able to approximately see where the poles and zeros are. But sometimes I would like to know the exact locations of poles and zeros. Is there a way to print out all the poles and zeros?
I know pz analysis can show poles and zeros, but in a feedback system I need to break the loop so that what pz analysis shows are the real open loop gain poles and zeros. So how to break the loop in pz analysis? I know stb has this built in...
thanks for helping.
I'm working on a design in OrCAD Capture 16.5. When making a netlist, I got errors because one of the part instances used an invalid footprint name (had a space in it).
I went into the part library and fixed the footprint naming. All I need to do now is update the instance in my design to reflect the updated source part in my library.
I found the part in my Design Cache and have tried "Update Cache" on the part (which succeeded without errors). The footprint field didn't get updated, however, on my part instance. I even tried "Replace Cache" without any success in updating my part instance...
Am I missing something here? How can I apply the updated cache to actual instances of parts in my design??
I can place a new part (from the source library or from the design cache) and it shows the correct footprint. I just can't get it to apply to existing part instances.
Hi,
I wrote an ocean script which has to do lot of simultations. It is working perfectly well but I would like to increase its speed. Currently I use run( ?jobName jobname ?queue lsf_queue ?mail nil ) to launch the simulations, and the following environnement variables:
envSetVal("asimenv.distributed" "removeJobData" 'boolean t)
envSetVal("asimenv.distributed" "showMessages" 'boolean nil)
The simulation launching time is about 7s/sim (everything is lauched sequentially) and ocean returns:
Delete psf data in /path/blablabla/HSPICE/schematic/distributed/7703/psf.
submitting job...
Does anybody know a way to decrease this launching time or to launch several simulation in the same time?
Thanks.
Thomas
Hi All,
In my skill programme, I would like to excute shell command like --> grep -w "Rule No." inputfile.txt > outputfile.txt
so i written programme like-->
--------------------------------------
k1="inputfile.txt"
k2="outputfile.txt" ;k1 & k2 are variables
k=buildString(list("grep" "-w" "Rule No." k1 > k2))
sh(k)
-----------------------------
But it prints like --> grep -w Rule No. inputfile.txt > outputfile.txt.
but i need to execute this command with word "Rule No." in quotations.
Please help me on this
Thanks in Advance,
Narendra
Hi,
I am trying to compare two layout views of a same cell. For this I am using the design sync function dssCompareViewsP(). But this fuction only reports the differences in the layers, nets, terminals and instances. The function is skipping the vias present in the layout, thereby the fuction is not comparing the whole layouts exactly.
Is there any other method/function to achieve this?
Regards,
Jay