Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place.
My question is: when I change the multiplicity or the number of finger in a FET transistor, it means I'm putting them in parallel.
My question is how I put them in series, without doing it manually.
Thanks.
For example I can have some HDL design compiled and implemented in Encounter Digital Implementation, then I can have that design imported in Virtuoso Encironment as a layout or higher level schematics symbol to be used together with another part of design which is analog.
However, which simulator is it better then to use to simulate the whole thing, by whole thing I mean my relatively big autoplaced/autorouted digital block from encounter + Hand made analog circuits?
For example if I want to just verify my analog-only blocks I'll use spectre, if I want to verify my digital logic and run timing analysis I'll use RC compiler + INCISIVE. But what about combined circuits simulation?
Obviously, using Spectre would take like infinite time (I remember simulating relatively small hand made digital circuits together with analog blocks, it took forever).
So which simulator, or approximate design/simulation flow should I look at then?
thanks
I am having trouble installing IC615 on ubuntu 13.10 (64 bit). When i try to run iscape.sh i get the following error
Exception in thread "main" java.lang.UnsatisfiedLinkError: /home/Thorin/Downloads/InstallScape/iscape.04.21-p004/runtime/LNX86/lib/i386/xawt/libmawt.so: libXtst.so.6: cannot open shared object file: No such file or directory
at java.lang.ClassLoader$NativeLibrary.load(Native Method)
at java.lang.ClassLoader.loadLibrary0(Unknown Source)
at java.lang.ClassLoader.loadLibrary(Unknown Source)
at java.lang.Runtime.load0(Unknown Source)
at java.lang.System.load(Unknown Source)
at java.lang.ClassLoader$NativeLibrary.load(Native Method)
at java.lang.ClassLoader.loadLibrary0(Unknown Source)
at java.lang.ClassLoader.loadLibrary(Unknown Source)
at java.lang.Runtime.loadLibrary0(Unknown Source)
at java.lang.System.loadLibrary(Unknown Source)
at sun.security.action.LoadLibraryAction.run(Unknown Source)
at java.security.AccessController.doPrivileged(Native Method)
at java.awt.Toolkit.loadLibraries(Unknown Source)
at java.awt.Toolkit.<clinit>(Unknown Source)
at com.khanpur.installer.gui.InstallerUI.main(InstallerUI.java:107)
Does anyone have an idea how to solve this? Should i install ubuntu 12.04 instead o 13.10 since 12.04 LTS in more stable or even try 10.04 LTS (32 or 64 bit)?
Also is have intalled java openJDK 6 and 5
Respected mam,
kindly help by consedering this cadence Simulation error i'm getting
version Virtuoso 6.1.5
What possible changes i can make for resolving the erronious simulation
Please reply at my official Em id: aceshivam99@gmail.com
{{ Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.
Error found by spectre during DC analysis, during info `finalTimeOP'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.
Analysis `finalTimeOP' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile. }]
Thanking you
Best Regards//
SHIVAM MISHRA
M.Tech - VLSI DESIGN
4th Sem Student @ SRM UNIVERSITY
TamilNadu, India
Hello all,
I got error message in LVS in parameters mismatch tool(Virtuoso XL), the message is :
Err: Sch MOS missing params: l,w ; Lay MOS W/L/NF 5e-06 1.8e-07 12
I don't have any idea about what this error means.If anyone has any idea about it then it will be a great help. Thank you.
Hi,
I am new to the reuse design concept.
Is it possible to use the 4 layer stackup reuse module(*.mdd) in 8 layer stackup or 10 layer stackup board without chaning the reuse module stackup?
Thank you
Hi everybdoy,
is it possible to extract the parasitics of a layout only for some parts of the hierarchy?
E.g. I would like to extract the parasitics of the "top level" and the level below to see the parasitics of certain (very long) wires. Further I would like to use the extracted view to include these parasitics into a simulation. The "sub cells" sould be included as normal schematics in the simulation.
I tried with the HRX, but with my settings this generates the sub blocks as extracted views in an additional library...
Thank you very much!
Best regards,
Markus
It would be useful to be able to rotate the global design space angle, allowing sub-groups of components to be routed while placed on an odd PCB.
For example: a group of components are rotated at 30 degrees, but all at 90/45 degrees to eachother. If one could rotate the design space (makes no changes on the design data) to 30 degrees, the pad entry cleanliness / alignment grid / line lock features could be used for the odd angle subgroup. This would be in place of routing the subgroup before rotating and placing into the PCB space alotted for the group.
This is also a problem when drawing dynamic shapes around pads when components are at odd angles, if one could rotate the design space to 30 degrees, the standard 45 degree line lock could be used while the design is rotated.
The feature would be adjacent to the 'move origin' area within the Design/Command Parameters menu, and would not change the design in any way (similar to moving the origin around).
EDIT: my assumption is that this feature does no exist (if it does, please, where?)
Regards,
PH
Hello,
I would like to netlist a device D1 with a parameter named P1 with two values A or B (theses values are straings).
In the CDF of the device I defined a string parameter P1 with two values A or B
For Spectre the job is well done: D1 P1=A.
For an other simulator I need to netlist D1 P1=str('A').
I try with paramMapping in the CDF but it seems not the good approach, is there any solution to do so.
Regards,
Fabrice
For some reason when I am routing Allegro will not snap to a cline. Vias and pins work but it refuses to snap to a cline.
Hi,
In the IGBT section of the reference manual the following literature reference is given:
[1] G.T. Oziemkiewicz, “Implementation and Development of the NIST IGBT Model in a SPICE-based Commercial Circuit Simulator,” Engineer’s Thesis, University of Florida, December 1995
Does anybody know where I can access this document?
Thanks in advance and best regards,
Nick
Hello.
I'm trying to generate a Schematic from a Netlist file on IC5141. Although I can successfully import the Netlist file and actually generate the Schematic, there is a problem with the devices' Width and Length.
For example, in my Netlist I have the following:
MM1 Q QN vdd! vdds! psvtgp w=0.135 l=0.06 nfing=1 sense=0 ngcon=1 m=1
+ accurateFlow=0
However, once imported, the device apparently doesn't reads the W and L values and sets it to 0 in the Schematic.
My device-mapping file looks like this:
devMap := nfet nsvtgp
termMap := D d S s G g B b
propMap := W w L l
devMap := pfet psvtgp
termMap := D d S s G g B b
propMap := W w L l
Any ideads as to why this is happening? I've been looking for a solution for this for the past couple of days and, thus far, haven't been able to find one.
Thanks in advance,
Michel Arendt
Have a question about the pad size?
I am new about Cadence design. And now, I am making a footprint for a part. The pdf file shows you the min/average/max of each pin.
when you make a footprint, which number are you going to use? I know the bigger pad the better, but I still want to run tace between pins.
For example,e1 could be 8.20-0.55 =7.65mm or also could be 7.40-0.95=6.45mm. that makes a lot of different about the footprint~~
all also each pin width, should I use0.22 or 0.38 or ?
Thanks
Hi,
I'm attending a stage in STMicroelettronics. I have to realize a digital filter IIR, for thr firts simulation I can't use any HDL. Then, I have to realize a filter using a LUT, when I'm using the flip flop to store my variable. I calculated the value of moltiplication with matlab script.
I have 100 value. The question is....
How to insert a file conteining this value from a text file? Or better, how to insert Design Variable containedin a file in Analog Design Enviroiment tool?
Thanks!
Hi,
When i'm trying to create a wire in Schematic editor of cadence Virtuoso
i'm getting the following error and wire is not getting created.
I'm able to copy/move/extent the already existing wires though..
"Loading layers.cxt
* Field is "color" *
*Error* hiCreateCyclicField: value must be contained within the list of choices"
It was working fine till yesterday.
If anyone know the solution/fix for this problem, please let me know..
reagrds,
Shameel