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Problem highlighting part

November 29, 2012, 2:34 pm
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We recently  did our first design using Allegro version 16.5 and I am having problems highlighting parts when using the viewer of the same version. 

 In the past I could zoom in anywhere on the PCB, click the "I" icon then use find to locate the part by refdes and the highlighted part  would  jump to the middle of the display. 

With the new version this does not happen. What is does now is zoom out so you can't find the part.   I can open 16.3 PCBs in the 16.5 viewer and it works like I just described above where the part jumps to the center screen with no change in zoom.  Has anybody else seen this behaviour? 

I'm just the guy trying to debug PCBs in the engineering lab and this is one of the most important features I use and now it's broke....

I showed our PCB designer and she did not know how to make it work either. 

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Viewing a shell ascii file and creating a shell path

November 29, 2012, 8:24 am
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I am using the view() function to open an ascii file from the shell, but it opens the file in the form/window in Virtuoso looking at the tail end of the file.  EG if the ascii file is larger than the viewing window, the contents scroll down to the end of the file.  Is there a way to use view() to open an ascii file but have the first view in the Virtuoso window remain at the head end of the file so the user can then scroll down instead of up?

Also, how can we create a path to write to a file location and pull from a specified path location by getting a path string from dbFullPath() and modifying it?

I am creating a new file using the cell name retrieved from geGetEditCellView()->cellName, but want to write to the same path location returned by dbFullPath() - with the exception of the last directory location.

For example, dbFullPath() returns ".../MyLibrary/MyLayout/layout/layout.cdb"

I create a file called "MyLayout_newfile" and want to write to ".../MyLibrary/MyLayout/MyLayout_newfile"

How do I truncate the end of the path returned by dbFullPath() - losing the "/layout/layout.cdb" portion?

 

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getting the label at tree view

November 29, 2012, 10:42 pm
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Hi everyone,

I am currently working on an interface where treelist is used. the form will display list of layers present in the design in tree list. every item is set to be displayed with a check box.. the main purpose of the check box is to serve as a trigger for another form.. but in order to load the form, the condition is to check the checkbox and then retrieve the label of item selected.. To retrieve if the checkbox is checked is quite simple, I just used form->treeViewSelState . what is quite confusing is how to retrieve the label whenever the checkbox is selected.. whenever i use form->curValue or axlformGetField. the label extracted is either nil or "". refer to the code below as reference

;;;;;code used to load items on tree list. note: DESIGN_LAYER_LIST is the list of layers extracted from board

(foreach item DESIGN_LAYER_LIST
          axlFormTreeViewAddItem(form "treeLayers" item nil nil t)
)

;;;;;code for form event

(case oForm->curField

("treeHandler"
   let(()
    (form->event
     (normal

        ;;;;; retrieve checkstate

           form->treeViewSelState

     )

)

)

)

Thanks in advance

      

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How to clear DRC or LVS highlights in Layout editor window ?

November 29, 2012, 11:06 pm
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Hi,

I m new to SKILL. Can anybody suggest me for how can i clear DRC or LVS highlights in layout editor window(in cadence virtuoso) using Skill programming.

Regards,

skulkarn

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Error while trying to explore about get_inst_coverage

November 29, 2012, 11:29 pm
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Hi,
I'm trying to observe the difference between get_coverage & get_inst_coverage with the following example;

class trans;
rand logic wrd;
rand logic [2:0] addr;
rand logic [7:0] din;
rand logic [2:0] no_of_rst;

covergroup cg;
type_option.merge_instances = 1;
option.per_instance = 1;
option.get_inst_coverage = 1;
op_t: coverpoint addr;
op_r: coverpoint din;
endgroup

function new();
cg = new();
endfunction : new
endclass

program main();
trans trans_0 = new();
trans trans_1 = new();
trans trans_2 = new();

initial begin
trans_0.randomize();
trans_1.randomize();
trans_2.randomize();
trans_0.cg.sample();
trans_2.cg.sample();
$display("coverage:%f",trans_0.cg.get_coverage());
$display("coverage1:%f",trans_2.cg.get_inst_coverage());
$display("coverage1:%f",trans_2.cg.get_coverage());
end
endprogram

But the cadence 10.20-s104 tool is showing error at lines type_option.merge_instances and at option.get_inst_coverage.

Can anyone suggest me the how can i get the get_inst_coverage result which is different from get_coverage?

Thanks,

Regards,

Mahee.

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Breaking down foot print libraries into categories

November 23, 2012, 6:07 am
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I find the one big footprint library very cumbersome. Has anyone broken theirs down into sub categories, ie; resistors, capacitors, ic's, etc..... If so are there any special constraints for the directory structure?

Do the padstacks need to be resident in the footprint library directory, or can I have a padstacks directory seperate from the footprints?

I would think I'd have to do something with the paths in order to make Editor locate the new sub directories, right? 

Thanks,

 Tom

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Voids areas on plane that won't go away

November 30, 2012, 10:30 am
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In the attcahed picture I have some void areas in the gnd plane that I can not get rid of. I have tried turning all colors on to see if there was somthing hiding there, but nothing shows up. Screen redraws and closing / re-opening board file have no effect.

What are these mysterious areas and how do I get rid of them?

Tom

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Cross section of .brd for import to Ansys / Percentage of Copper per layer

November 30, 2012, 9:04 am
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Hello,

      I have been asked to provide a cross section / cutt-out of a .brd to send to Reliability Engineering for import into Ansys for Thermal Analysis.  Is there a way to cutt away unwanted sections of the design quickly?  The area of interest is under the package of a large BGA. 

      I am also interested in percentage of copper on each layer under this package.  I have ran a film area report, however the reported numbers are not in allignment with my manual calculations used for verifying the reports accuracy. Any ideas? Any and all help would be greatly appreciated.

Thanks,

Clint

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Connecting symbol shapes to internal layer

November 30, 2012, 6:24 am
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On the connector shown below I want to connect the shapes around the perimeter to the internal gnd layer. I have selected each shape and assigned the net "gnd" to each but I get no ratsnest showing a connection needs to be made. The status command does not show them as unconnected either.

Previously I would have edited the copper area to assign the net, then placed a "free via" to connect to the gnd plane. I don't see a method to get a small hole into the shape.

I tried to add pins to the library part, but that requires adding additional pins to the schematic symbol. Plus, can you even have a pin inside a shape?

Tom

(I sure picked the right avatar........)

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OrCad CIS on mySQL server

November 30, 2012, 11:55 am
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I am using OrCad CIS 16.5 and I would like to use my company server to host the CIS database. We are using mySQL. I have set up a database with the properties as described in the help and created a new odbm data source. However, if I want to create a new data source in OrCad CIS preferences it doesn't appear in the options. I was wondering if OrCAD accepts mySQL as data base? Does anyone have a document how to set up the database on mysql and integrate it into OrCad CIS?

Many thanks in advance.

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Running DIVA extraction in batch mode for IC5.14

November 30, 2012, 8:04 am
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Hi,

 I am trying to extract parasitics of a layout. I am wondering how I can invoke DIVA extraction in shell?

 Thanks,

Reza

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noise on bits of same bus

November 30, 2012, 5:19 pm
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 Hi All,

 Iam working on cross talk analysis of mixedsignal  design . and the SI analysis will do noise on delay and glitch noise analysis. 

In my deisgn , the bits of bus are custuom routed and as per ETS tool , i dont have noise on delay issues. But , the tool shows  glicth issues between the bus bits, i.e. it was shown that aggressors and victims are of same bus. 

1) Can you suggest whether it can be waived off  or not ? 

2)  I have gone through some paper which says ,  aggresors and victims of same bus are accounted for noise  delay and does not effected due to  noise on glicth. I did not understand this ? can any one share your taughts on this.

3)  If it can be waived off , please share the reasons.

4) If they can not be waived off , pease suggest me some work around. Because, these bits of a bus from one macro to another 

macro and there is no space also to increasing  between the bus bits.

 

Regards,

K.VISWANADH BABU

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Identical circuits BUT completely different device behavior

November 30, 2012, 8:49 pm
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Ok, so somehow magically (why the calculations and theory does not match with the pspice model is another post) a circuit begins to work in a project. So I copy this circuit over to a new project (to preserve the parameters and settings of the devices because one is becoming increasingly unsure of reproducing the same results in pspice given a set of parameters).

 The circuits I am attaching are IDENTICAL very basic common source amplifiers with active loads. 

 1)

https://docs.google.com/open?id=0BwG45lg3wcwnU3ZDQ3NtNjZCM2s

  Project_Working with 1000 Gain-Nov-30-2012.zip is a file that has the original circuit which gives an input signal of 1mv an amplification of 1000 (to around 1V).

2) 

https://docs.google.com/open?id=0BwG45lg3wcwnWml3UFVMQ0dxekE

P2_First_Stage_Working-Nov-30-2012.zip is simply a new project into which I have copied and pasted the circuit from above (nothing changed except adding the .lib files in configuration. BUT the amplifier mosfet (the one at the bottom) is now displaying completely different device traits. 

 

3) If I force a drain current into an n channel mosfet which forces the mosfet into saturation I should NOT have to bias the mosfet further right ? YET I have to do this here where I supply a dc voltage and get an n channel mosfet into the saturation region by observing the VTC traits (Vds vs Vgs graph). Then I go back and give the right dc voltage to bias the amplifier in the right region. I am fairly new to CS amplifiers but my professor was surprised that it needed a bias voltage + an active load.

 p.s if someone could also explain why pspice is prone to magical charms that would be very cool even though it SHOULD not be because one happens to encounter some bad people (and one has lived a very long time to have met such misfortune) who somehow can affect the operation of a model (does this make sense)? one is totally embarassed about mentioning this but for a long time one suffered at the hands of such people without knowing it and now (only lately) has one begun to recognize this odd and terrible thing.One sincerely hopes one is spared the proximity of such a people (is this a professional hazard ; if so which profession would enable one to be independent and safe from such practices)

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Editing symbols

November 30, 2012, 7:28 pm
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Greetings,

A newbie here. I have used Orcad for a very little while, so a learning curve. I placed a transformer on the page, and want to remove the "pin numbers' from the symbol. How do I go about this? I have done the right click on the lead, then edit properties, hihlighted the "name" colum and get lost after that. I have tried to find the answer in the help menu, but....

Please, HELP!!

Thanks 

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Connect macro power to top level

December 7, 2012, 12:08 am
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Hi,

I have read alot about this issue (in this forum), but still don't having some problems.

i have power strips + power ring  in my block, and i use lefOut -stipePin in my block to generate the lef file for top level.

i can see in the lef file the power & ground  port  (also see "use power" & "use ground", and a list of "RECT" in top layer).

the problem is - i can't connect my top power strips to my macro block.

i use the "globallnetconnect"  in my top level & in block level with the same names.

the thing is when openning my top level and reading the lef, i can see the block pins but not the VDD & VSS ones.

any idea?

thanks!! 

 

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To add skill files to the taskbar

December 6, 2012, 2:05 am
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 Hi all,

 How to add skill files in the menu bar?

Please explain what steps to be followed?

 

 

Rajan

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Error on NC drill (by layer) output file

December 7, 2012, 6:14 am
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Hello,

I am designing a 4 layer board with some blind/buried vias. So on “Manufacture -> NC -> NC Drill” I selected under “Drilling” the option“By layer”. There are then generated 3 output files “file-1-2-np.drl”, “file-2-3-np.drl”and“file-3-4-np.drl”.

In order to probe if everything was all right, I placed on the board 4 mounting holes (the same symbol four times), but on the output files 1-2 and 2-3 I got

 

X17000Y-17000

X-17000Y-17000

X-17000Y17000

 

While on the file 3-4 I got

 

X17000Y-17000

X-17000Y-17000

X-17000Y17000

X17000Y17000

 

So, one of the hole is only visible on the last layer; something like a blind via but it is actually a passing though hole. I repeated the process several times and the output was always the same. In fact, I discovered that the last hole that I place on the PCB is the one that has the error on the output files. If I choose the option of “Drilling” “Layer pair”, the output file is correct.

Am I missing some configuration? Or maybe am I doing something wrong? Any ideas?

I’m using Allegro PCB designer 16.5

Thank you very much.

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Cannot add pins to a block....

December 7, 2012, 3:39 am
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I am encountering a problem adding pins to a block. Oddly this is only affecting the right hand side of the block (the output side).

I can add pins (Add Pin>type the pin name> click on the block at the particular location) on the left hand side but the pins refuse to be placed on the right. Oddly on the right hand side of the block there is a pin with no name attribute shown, which i have attemped unsuccessfully to delete. How this came to be here, i do not know (i am a newbie), but i suspect this may be preventing the placement of pins.

How do i remove the unidentified pins?

How do i interrogate the block to identify why i can't attach pins?

 Any help would be appreciated

J

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4 layer design stackup

December 7, 2012, 5:32 am
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Anyone doing this with ground on layers 1 & 4 and signals on 2 & 3?

Surface mount components on one side or both sides.

Pro's and con's?

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Transistors in series

December 7, 2012, 8:57 am
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Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place.

 

My question is: when I change the multiplicity or the number of finger in a FET transistor, it means I'm putting them in parallel.

My question is how I put them in series, without doing it manually.

Thanks. 

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