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How to create pad for SMD parts

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Hello,

I'm really new to the OrCAD layout and know nothing about this before. I'm sorry if there is any dump questions from me :)

I'm try to create a foot print for this part.

 

1. First question is: As I understand that to create this footprint I first need to create the 0.40 x 1.22mm pad right? 

To create the pad I learn that I need to used Pad Designer. I also have have couple questions about this as well.

 

2. What informations I need to enter in the box 1, 2, and 3? What do they mean? Is there any book teaching about this? I would like to buy one to read. Or any guide that show how to make a simple SMD pad.

 

3. For SMD pad, I just need a Single layer mode???

Please help a newbie out. Appreciate for your help.

 


Declaring global net in schematic composer

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 Dear All,

I want to name a net as global so that it can be accessed in the hierarchy.

But also I want the same net should not be created as a PIN in layout.

Could anybody please tell how that can be achieved ?

Kind Regards,

How to generate a list of display layers?

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Hi,

 I am using cadence virtuoso version IC6.1.5-64b.500.17. I would want to generate a list of layers that is already displaying in my Layout editor window.

 I already know there is a function call leLSWShowLayers(), but I am not using LSW. I am using layer palette. And I can't bring LSW up using leRaiseLSW() because my palette assistants are enabled.

 I can't use the solution in solution 20268008 by using pteRegisterUserSelectionTrigger because my cadence version isn't new enough.

 Please let me know what other ways I can produce a list of displayed layers?

 Thank you.

KokoLiu 

Change a copied via net and via arrange

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Hi,

I have copied some vias from other routed nets. I have a problem and that is I can't find anywhere to change this copied vias net property!.. Could anybody please help?

I am also going to align some vias vertically or horizantally. If I go to placement edit mode I'll see that I can't select vias like symbols to align them or change space between them?!..

I would appreciate any help.

Hossein

Question on Schematic Porting from X-Foundry PDK to Y-Foundry PDK

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Hi,

I am trying to make a schematic conversion from X-Foundry PDK to Y-Foundry PDK.

I found the skill codes "abConvertComponentParams" by Andrew very helpful.

However, I have two questions below that would need some quidences:

(1) How to remove unwanted CDF properties in the original symbol of X-Foundry?

     After the skill code conversion, some CDF properties become user properties in the new symbol.

     Those proporties are specific to X-Foundry and it would be better to remove them during the conversion.

     Specifically, it would be even better to just map the parameters specified in "conv.config" only and remove all other parameters. 

(2) How to map a parameter type of "string" to type "integer"?

     The example fixIt procedure seemed to return a string and caused the following warning message:

      *WARNING* Invalid type (string) for property 'segments' on instance 'R1'

Any help/suggestions would be much appreciated.

Thanks.

Ethan

Z state check inside SV

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I am using cadence irun to run the mixed signal verification. I am trying to see if real value i am getting is has open drained or not. How do I check Z state of real value in testbench. 

how to pass the windowid number to the assistSlider

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Hi guys,

I was try to write a skill code to toggle assistants like navigator. 

 Now I used the hiGetCurrentWindow() to get the windowid, say window:25, but I'm stuck here. If I can pass the number to get assistSlider25 then I can set the parameters of this guy to turn on and off all the assistants.

Anyone has idea how to pass this number?

 Thanks

Xiangyong 

How to override Rule-deck default FilterOptions in ASSURA

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 Dear All,

In my process compare.cdl file, some default filterOptions are there.

I want to override them (i.e. I don't want the ruldeck FilterOptions() to be used).

Is there any way I can do that in ASSURA ?

Kind Regards,

 


32n finfet vs 32n mosfet simulate

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Somebody help me?
I want to simulate a paper but it does not similar paper 

hal.inria.fr/docs/00/74/92/05/PDF/25.pdf 
 
I download transistor model (Mosfet32n h/k and finfet32n) from the site. Ptm., But I do not know what changes should do it 
on both: w=100n l=32 vin=0.5
My result with this models: Avgpwr mosfet was better than finfet. but delay for mosfet  too beter then finfet
But this result is wrong. : (((

delay finfet should be beter

help help help help help help :-( :bang:

Cheap K'i't'c'h'e'n's' Sale Leeds

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Cheap K'i't'c'h'e'n's Sale Leeds. Thirty Ex Display K'i't'c'h'e'n's To Clear. w'w'w'.'e'x'd'i''s'p'l'a'y'k'i't'c'h'e'n's''1'.'c'o'.u'k' £ 595 Each with appliances.Tel 01616-694785

regarding metal overlap shape

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Hi,

 

I want to put the auto via between metals through skill. I am able to calculate the intersection area through layer AND operation .But i am not able to calculate that which metals are available in the area.  Like If I know that M1 or M2  or any combination of metals are there then only I can put the corresponding via. Kindly help me in this. 

 

 

 

How to execute a skill script at command line

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Hi,

I written a skill script which creates a widget, I want to run this script at command line. How to do this. And Is there any way to execute skill script with out opening the tool.

Thanks,

Harish.

Convert *.sch from old version of OrCAD

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Hello all!

I have found a lot of sch. files, made in very old version of OrCAD - v1.25 (1985-1987 years). Also I have this version OrCAD with all libraries, and all work fine under DosBox emulator. I have two question:

1) Is it possible to convert from sch OrCAD v1.25 into any other modern file format?

2) I can write my own file convertor if will know the structure of .sch and .lib files in OrCAD v1.25. May be possible found somewere this information?

Eagle to orCAD?

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I have some Cadsoft Eagle 6x designs.

Are there any tools that would hekp me convert schematics or board files?

Create Netlist removes some net members of a Net-Class

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Hi,
I am working with Allegro PCB 16.6. I see a very strange phenomena in my design. When I try create netlist in Capture and load it to *.brd file I see that it has removed some net members of a defined net class?!. :-( I don't see why and how this can happen. Can anybody please help?!
Thanks all,
Hossein

Change a copied via net and via arrange

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Hi,

I have copied some vias from other routed nets. I have a problem and that is I can't find anywhere to change this copied vias net property!.. Could anybody please help?

I am also going to align some vias vertically or horizantally. If I go to placement edit mode I'll see that I can't select vias like symbols to align them or change space between them?!..

I would appreciate any help.

Hossein

Configuring new PDK

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I was configuring the new PDK in Cadence virtuoso version IC6.1.4.500.12( one PDK is already existing in the home directory). so i make a new folder(named "new_PDK") in the home directory and added the files(cadence.cshrc, cds.lib, .cdsinit, .cdsenv, bindkeys and the PDK folder). when i source the cadence.cshrc file from from folder new_PDK, i am listing out the problems i am facing:

 

1. its shows techfile conflict

" there is a conflict in techfile graph

  Look at techfile reported error massage in CIW

  correct techfile conflict before proceeding "

 

  Whill loading the files, it takes techfile.tf, pdkutil and display.drf file from PDK folder olny.

 

2. In the schematic window, i can call the instances but unable to connect using wires(wires are not coming. rest all shortcut keys are working.

 

3. In the layer selection windows(LSW) palletes are not visible.

" (LE-101804): Cannot get valid layer form LSW window. "

 

   i can see the layer when i click on layer but again shows blank when i scroll it down.

 

4. Cadence windows crash when i try to make any layer in the layout.

"  \o (LE-101804): Cannot get valid layer form LSW window.
   \a leSetLSWBBox(list(57:328 207:1028)) "

 

Everthing working properly with the old PDK exist in home directory.

 

Please help me out.

 

How to close a netlist in Ocean

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I’m running an ocean script that runs multiple PVT corners in a nested foreach loop (see sample below). It runs all the PVT corners in parallel using LSF.

The problem I’m having is that at each corner, the run generates a netlist. With post-layout extraction, the netlist could be ~100M, and soon enough, Ocean runs out of memory.

I want to ask if there’s a simple command I could use to close the netlist before proceeding to the next iteration of the loop. That way Ocean doesn’t run out of memory just submitting jobs to the LSF queue.

Pseudo-code:

-------------------------------- 

foreach(corner cornerlist

foreach(vdd vddlist

foreach(temp temlist

run(?jobName job ?drmsCmd bsub_cmd)

); end foreach templist

); end foreach vddlist

); end foreach model 

How to implement soft reset or functional level reset in vr_ad register model?

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Hi all,

In my project in the register model i have some fields which are sticky i.e. they are not effected by reset.For such fields how to implement in vr_ad? If it is possible, is there any chance to implement dircetly from the IPxact script(With the help of verdor defined extensions)?

 Please help me in this regard.

Thanks in advance,

Subhash. 

Can assign a net to a pin in Allegro PCB

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Hi,

I have an FPGA  in my design with some unused pins. I am wondering if I can assign a net to pins in Allegro PCB and then update schematic. I would appreciate any help on this issue.

Thanks,

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