Source for 90nm library?

August 19, 2014, 2:55 pm

≪ Previous: how to link the CIS Part manager with a database Microsoft access (.mdb)

Hello togehter!

actually, i'm at a very starting point with my project (PhD student): i'd like to re-design a logic cell of the well known Spartan 3A FPGA. This is no big deal, since it consits only of 2 look-up tables, 2 latches und a bunch of multiplexers (ok, by looking on the schematics it's a tad more complicated, but that's no so bad anyway).

I have access to Virtuoso Design Environment IC 6.1.5, but i have no idea where i could get a tech lib for 90nm from (the Spartan 3A FPGA was designed by using a 90nm process)...can anybody give me a good advice or hint please?

Is it possible to get a 90nm tech lib "for free" (i really don't belivie that, but i wanted to ask for it anyway :-) ) or are there any other possibilities how i could proceed.

Many thanks in advance!

Karol

↧

[Help] Problem on LVS

August 19, 2014, 10:09 pm

≫ Next: NanoRoute crash with incremental tech libraries in mixed signal flow

≪ Previous: Source for 90nm library?

Hi,

I am doing the LVS, and I encounter a problem. Thank you! And the following is the file:

Assura (tm) Physical Verification Version av4.1:Production:dfII6.1.3:IC6.1.3.500.10
Release 4.1

Copyright (c) Cadence Design Systems. All rights reserved.
@(#)$CDS: assura version av4.1:Production:dfII6.1.3:IC6.1.3.500.10 06/09/2009 14:40 (sfrh259) $
sub-version 4.1, integ signature 2009-06-09-1330

run on ee308-09.nmsu.edu from /opt/cadence/ASSURA41/tools.lnx86/assura/bin/32bit/assura on Tue Aug 19 23:01:27 2014

Starting /opt/cadence/ASSURA41/tools/assura/bin/aveng /home/graduate/qshu/IBM_Design/sub_LNA_outres.rsf -exec1 -LVS -cdslib /home/graduate/qshu/IBM_Design/cds.lib
@(#)$CDS: aveng version av4.1:Production:dfII6.1.3:IC6.1.3.500.10 06/09/2009 14:41 (sfrh259) $
sub-version 4.1, integ signature 2009-06-09-1330

Starting dfIIToVdb...
@(#)$CDS: dfIIToVdb version av4.1:Production:dfII6.1.3:IC6.1.3.500.10 06/09/2009 14:44 (sfrh259) $
sub-version 4.1, integ signature 2009-06-09-1330

run on ee308-09.nmsu.edu from /opt/cadence/ASSURA41/tools.lnx86/assura/bin/32bit/dfIIToVdb on Tue Aug 19 23:01:28 2014

Loading IBM PDK cmrf7sf procedures...
IBM PDK cmrf7sf Device Status Table loaded.

*Error* eval: undefined function - hiGraphicMode
<<< Stack Trace >>>
hiGraphicMode()
(getd('dbGetDatabaseType) && (dbGetDatabaseType() == "OpenAccess") && (hiGraphicMode))
...
Compiling rules...

WARNING LVS Run detected.
Non-legacy mode has been disabled for this LVS run
Checking out license for Assura_DRC 4.10

Reading the design data...

Finished dfIIToVdb.

Building the VDB part 2 in background mode.

Building tables for LVS Preprocessing in background mode.

Starting /opt/cadence/ASSURA41/tools/assura/bin/vdbToCells . sub_LNA_outres

Finished /opt/cadence/ASSURA41/tools/assura/bin/vdbToCells

Starting Nvn PreExtraction...

Starting /opt/cadence/ASSURA41/tools/assura/bin/nvn /home/graduate/qshu/IBM_Design/sub_LNA_outres.rsf -preExtract -exec1 -cdslib /home/graduate/qshu/IBM_Design/cds.lib
@(#)$CDS: nvn version av4.1:Production:dfII6.1.3:IC6.1.3.500.10 06/09/2009 14:45 (sfrh259) $
sub-version 4.1, integ signature 2009-06-09-1330
run on ee308-09.nmsu.edu at Tue Aug 19 23:02:15 2014
INFO (AVLVSNN-10120) : '.nocase' command in binding file also switches on softSearchDeviceName(t) option to ensure, that compare rules are applied correctly.
Reading schematic network
inputting netlist /home/graduate/qshu/IBM_Design/LVS/sub_LNA_outres.netlist.lvs
*WARNING* *.EQUATION is not supported
*WARNING* *.MEGA is not supported
*WARNING* *.PIN is not supported

*ERROR* on line 33 in file /home/graduate/qshu/IBM_Design/LVS/sub_LNA_outres.netlist.lvs
? expecting colon (:)
*.PININFO Vbn:I Vbp:I Vin
______________________^^^

Finished /opt/cadence/ASSURA41/tools/assura/bin/nvn

*WARNING* An error occurred during Nvn PreExtraction.
LVS preprocessing requires a successful run of Nvn.
Assura will now terminate.

*WARNING* /opt/cadence/ASSURA41/tools/assura/bin/nvn exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated
*WARNING* Bad exit from child process .. 0x100

***** aveng terminated abnormally *****

***** aveng fork terminated abnormally *****

*WARNING* aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated

↧

NanoRoute crash with incremental tech libraries in mixed signal flow

August 19, 2014, 7:33 am

≫ Next: Change a copied via net and via arrange

≪ Previous: [Help] Problem on LVS

I'm trying to create an incremental technology database tree for using the ARM 7-Track Standard Cell library for the Global Foundries 130nm BCDlite process. My metal stackup is 8 metal layers with two top metals. I only want to use 5 metal layers (all signal layers) for digital implementation, but want to embed it in a design using the real stackup.

For our pure digital flow, we typically load the ARM routing technology LEF (sc7_tech.lef) and the standard cell LEF (sc7_130bcdlite_base_rvt_w3.lef), and proceed with Encounter for full implementation. This works fine.

Now, following the guidance of the Mixed Signal Interoperability guide, I'm migrating these LEFs over to an incremental tech library in OA. First, I import from the ARM 7-track routing technology LEF:

lefin -lef sc7_tech.lef -lib sc7_tech -techRefs gf013hv30v -mapConflicts

This gives me a library sc7_tech that references gf013hv30v. I then do this for the 7-track standard cell library.

lefin -lef sc7_base_rvt_w3/r0p0/lef/sc7_130bcdlite_base_rvt_w3.lef -lib sc7_130bcdlite_base_rvt_w3 -techRefs sc7_tech

This gives me the standard cells. My hierarchy, is thus sc7_130bcdlite_base_rvt_w3 -> sc7_tech -> gf013hv30v (the base PDK).

I'm able to load this OA into Encounter instead of the LEFs and use it as normal. However, when I run routeDesign, encounter stops at "start initial detail routing ...", and begins to fill up all of the memory on my machine (all 64 GB) before crashing. The exact same flow with the LEF files works without any problems.

I would really like to figure out why this is happening, and am confused that trialRoute is able to work fine with the OA library. I can even save the trialRouted design into OA and open it with Virtuoso, remaster instances, etc. It's just routeDesign -globalDetail that crashes it.

Some things that I've tried

Modify the sc7_tech LEF file to match my metal stackup (it uses 6 metal layers, with 6 being a top metal), based on info from the gf013hv30v techFile.
Modify that modified LEF to not include any info for MET7 or MET8.
Pull in the routing tech LEF using -pnrLibDataOnly

I also tried importing in sc7_tech.lef without referencing the base PDK. This worked and was able to get through the same Encounter flow as before without a problem. The issue is, of course, that the resulting layout is not referencing the base PDK that the rest of the design is, so all of the non METAL/VIA layers are gone, and it doesn't exactly match my stackup (i.e. not very interoperable).

Please help. We're expecting to tapeout very soon and this is blocking us.

Thanks!

↧

Change a copied via net and via arrange

August 20, 2014, 12:15 am

≫ Next: Problem in opening schematic file

≪ Previous: NanoRoute crash with incremental tech libraries in mixed signal flow

Hi,

I have copied some vias from other routed nets. I have a problem and that is I can't find anywhere to change this copied vias net property!.. Could anybody please help?

I am also going to align some vias vertically or horizantally. If I go to placement edit mode I'll see that I can't select vias like symbols to align them or change space between them?!..

I would appreciate any help.

Hossein

↧

Problem in opening schematic file

August 20, 2014, 1:14 am

≫ Next: creating a browse button to browse directories

≪ Previous: Change a copied via net and via arrange

Hi,

I am trying to open a certain op-amp design in schematic but it is showing warning and is not showing proper blocks of the op-amp may be some file is missing as it says, please tell me where to get those files and also how to include them in that library. I am attaching snapshot of the error.

↧

creating a browse button to browse directories

August 20, 2014, 2:32 am

≫ Next: EDI Placement Density Screens Honored after Optimization?

≪ Previous: Problem in opening schematic file

Hi,

How to create a button to browse directories. The user can able to select multiple directories, and the output should be of return type list.

Please tell me how to do this.

Thanks,

Harish.

↧

EDI Placement Density Screens Honored after Optimization?

July 1, 2014, 12:33 am

≫ Next: Binding systemverilog modules (module ports' directions)

≪ Previous: creating a browse button to browse directories

Dear All,

Can anyone tell me if Density screens are honored after optimization? I'm trying to applyplacement density screens in EDI 14 but they

are not honored after optimization.

Thanks,

Aram

↧

Binding systemverilog modules (module ports' directions)

August 19, 2014, 5:49 am

≫ Next: Can't place via next to pin

≪ Previous: EDI Placement Density Screens Honored after Optimization?

Hello,

I'm using some binding modules in sytemverilog VIP. They are binded to VHDL modules.

The systemverilog modules' ports are all defined as logic without specifying direction (input, output or inout).

Compilation passes without any errors. Elaboration fails. It requires direction to be specified for some ports in sys-verilog bind modules definitions as te direction for the VHDL modules.

This isn't the case with modelsim which doesn'r produce elaboration errors.

Also Why this is required for some ports and not all the ports ?

The error code is: ncvhdl_p: *E,CFMPMC

And an example on the eror msg is: "(./INCA_libs/irun.lnx8664.11.10.nc/.cdssvbind/cds_tmp_svbind0000422d_a8c0620a_0x2a003d41.sva,2|762): Port mode mismatch: Verilog(fsm_sink_bind.send_ack) is mode 'input'; VHDL(FSM.SEND_ACK) is mode 'out'."

Note that it says fsm_sink_bind.send_ack direction is "input", although I declare it as logic without specifying direction !

↧

Can't place via next to pin

August 21, 2014, 2:53 am

≫ Next: How to override Rule-deck default FilterOptions in ASSURA

≪ Previous: Binding systemverilog modules (module ports' directions)

Hi,
When I want to route some tracks of pins I can't place via just near the pin, while for neighbour pins I can do it easily. I have also defined a Power class net for both of them with pin to thru via spacing of 0.
Below picture clarify the issue better:

Thanks in advance,

Hossein

↧

How to override Rule-deck default FilterOptions in ASSURA

August 21, 2014, 5:05 am

≫ Next: Pin labels in Virtuoso from Encounter OA

≪ Previous: Can't place via next to pin

Dear All,

In my process compare.cdl file, some default filterOptions are there.

I want to override them (i.e. I don't want the ruldeck FilterOptions() to be used).

Is there any way I can do that in ASSURA ?

Kind Regards,

↧

Pin labels in Virtuoso from Encounter OA

August 20, 2014, 9:39 pm

≫ Next: How to execute a skill script at command line

≪ Previous: How to override Rule-deck default FilterOptions in ASSURA

I'm trying to get a mixed signal environment up and running. I can save the Encounter database to OA using an interoperable PDK (standard cell/routing tech lef in OA referencing base PDK). The layout looks fine in Virtuoso, but one thing that I am missing is pin labels (the kind I need for LVS). The wierd thing is that if I stream the design out from Encounter to GDSII and then stream it in, all of the pin labels are there on the proper layers. They just don't show up in the OA layout (doesn't matter whether I use saveDesign or oaOut).

↧

How to execute a skill script at command line

August 20, 2014, 8:19 pm

≫ Next: symbol to layout conversion

≪ Previous: Pin labels in Virtuoso from Encounter OA

Hi,

I written a skill script which creates a widget, I want to run this script at command line. How to do this. And Is there any way to execute skill script with out opening the tool.

Thanks,

Harish.

↧

symbol to layout conversion

August 20, 2014, 6:56 am

≫ Next: Setting time resolution using irun

≪ Previous: How to execute a skill script at command line

Hell0,

I am using lxGenFromSource(dbOpenCellViewByType(libName cellName "symbol" "" "r") ?layLibName newLib ?layCellName newcell ?layViewName "layout") to convert symbol into layout but I am getting the following warning

*WARNING* (LX-2031): Cannot find the specified schematic cellview. The name or database IDyou specified either does not exist or does not point to a validschematic cellview. Specify a valid schematic cellview and try again.

but I have this Symbol view in my specified cellname , What could be the problem ?

Thanks

farhan

↧

Setting time resolution using irun

August 21, 2014, 8:32 am

≫ Next: Reading PCell Properties/Parameters using SKILL

≪ Previous: symbol to layout conversion

Can I change time resolution using iruns scripts?

Command: irun -input setup.tcl

Script:

database -open waves -into xxx.shm -default -event

probe -create -all -depth all

run 2ms

Now I have got on my simvision waveform time resolution equals 1 ps.

↧

Reading PCell Properties/Parameters using SKILL

August 15, 2014, 1:45 am

≫ Next: How to append a label on a rectangle created by dbCreateRect()

≪ Previous: Setting time resolution using irun

Hello All,

I have a PCell that has nfet layout and I am writing a SKILL code to open the layout and label the Gate, Drain, Source and Bulk in layout. For that I need to read the parameters that where is the Gate, Drain and Sourcein layout. I tried some commands like :

pcGetParameters , pcGetParamLabelDefn, pcGetParamLabels, pcGetParamLayers but all of them are given me "Nil". Can anyone help me what's wrong ? Is it because the PCell doesn't have any properties ?

or is there any better way for labeling ?

Thanks

P.S: I didn't created that PCell and I am very beginner to SKILL.

↧

How to append a label on a rectangle created by dbCreateRect()

August 21, 2014, 6:36 am

≫ Next: Problem with Assura license

≪ Previous: Reading PCell Properties/Parameters using SKILL

Hi experts,

Using dbCreateLabel() could only create the label in cellview but not appended on a object (e.g. rectangle).

Is there any way that I could append a label on a rectangle (i.e. as a children of a rectangle) created by dbCreateRect() (but not rodCreateRect()) ?

↧

Problem with Assura license

August 22, 2014, 8:36 am

≫ Next: Changing bBox of cell using dbTransformBBox/geTransformUserBBox

≪ Previous: How to append a label on a rectangle created by dbCreateRect()

Hi,

After successful DRC and LVS verification RCX (C extraxtion) fails with the following error:

Assura (tm) Physical Verification Version av3.2:Production:dfII6.1.3:IC6.1.3.500.7

Release 3.2_USR2_HF11

@(#)$CDS: assura version av3.2:Production:dfII6.1.3:IC6.1.3.500.7 06/29/2009 05:57 (sjlin84) $

sub-version 3.2_USR2_HF11, integ signature 2009-06-29-0444

run on rose.eecg from /autofs/fs1.ece/fs1.vrg.CMC/tools/cadence.2000a/ASSURA-613.03.20.022.linux/tools.lnx86/assura/bin/32bit/assura on Fri Aug 22 11:34:54 2014

Checking out 1 license for Assura_RCX 3.10

ERROR (LMF-02018): License call failed for feature Assura_RCX, version 3.100 and quantity 1. The license server search path is defined as 7055@u10e.vrg.utoronto.ca:6055@u10e.vrg.utoronto.ca:/CMC/tools/licenses/cds.license:/CMC/tools/licenses/amslmd_v400.license. The FLEXnet error message is as follows,

FLEXnet ERROR(-18, 0, 0): License server system does not support this feature.

Run 'lic_error LMF-02018' for more information.

FLEXnet ERROR(-18, 0, 0): License server system does not support this feature.

Run 'lic_error LMF-02018' for more information.

ERROR (LMF-02018): License call failed for feature Virtuoso_QRC_Extraction_L, version 3.100 and quantity 1. The license server search path is defined as 7055@u10e.vrg.utoronto.ca:6055@u10e.vrg.utoronto.ca:/CMC/tools/licenses/cds.license:/CMC/tools/licenses/amslmd_v400.license. The FLEXnet error message is as follows,

FLEXnet ERROR(-18, 0, 0): License server system does not support this feature.

Run 'lic_error LMF-02018' for more information.

ERROR (LMF-02018): License call failed for feature Encounter_QRC_Extraction_L, version 3.100 and quantity 1. The license server search path is defined as 7055@u10e.vrg.utoronto.ca:6055@u10e.vrg.utoronto.ca:/CMC/tools/licenses/cds.license:/CMC/tools/licenses/amslmd_v400.license. The FLEXnet error message is as follows,

FLEXnet ERROR(-18, 0, 0): License server system does not support this feature.

Run 'lic_error LMF-02018' for more information.

Starting /CMC/tools/cadence/ASSURA-613.03.20.022.linux/tools/assura/bin/rcxToDfII /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/ASSURA_LVS/rail_comparator/rcx.rail_comparator.rsf -t -cdslib /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/cds.lib -libdefs /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/lib.defs

@(#)$CDS: rcxToDfII version av3.2:Production:dfII6.1.3:IC6.1.3.500.7 06/29/2009 06:01 (sjlin84) $

sub-version 3.2_USR2_HF11, integ signature 2009-06-29-0444

run on rose.eecg from /autofs/fs1.ece/fs1.vrg.CMC/tools/cadence.2000a/ASSURA-613.03.20.022.linux/tools.lnx86/assura/bin/32bit/rcxToDfII on Fri Aug 22 11:34:58 2014

Loading all available p-cell functions

AMS_DB set to cds

No mx check

ROD pcell code loaded

Finished /CMC/tools/cadence/ASSURA-613.03.20.022.linux/tools/assura/bin/rcxToDfII

Starting /CMC/tools/cadence/ASSURA-613.03.20.022.linux/tools/assura/bin/avRCXxref /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/ASSURA_LVS/rail_comparator/rcx.rail_comparator.rsf

@(#)$CDS: avRCXxref version av3.2:Production:dfII6.1.3:IC6.1.3.500.7 06/29/2009 05:57 (sjlin84) $

sub-version 3.2_USR2_HF11, integ signature 2009-06-29-0444

run on rose.eecg at Fri Aug 22 11:34:59 2014

Reading rsf

Finished /CMC/tools/cadence/ASSURA-613.03.20.022.linux/tools/assura/bin/avRCXxref

Constructing the RCX run script

*** ASSURA capgen VERSION 3.2 Red Hat Linux release 7.2 (Enigma) - (04/30/2009-14:21) ***

**********************************************************************

* *

* This software is the confidential and proprietary information of *

* Cadence Design Systems, Inc. and may not be copied or reproduced *

* in whole or in part onto any medium without Cadence's express *

* prior written consent. Unpublished rights reserved under all *

* copyright laws of the United States. *

* *

* Cadence Design Systems, Inc. *

*555 River Oaks Parkway *

* San Jose, CA 95134 *

* *

**********************************************************************

capgen Capgen results will be written to directory: /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/ASSURA_LVS/rail_comparator/rail_comparator

*ERROR* at "capgen": -res_blocking mask layer 'rblock_poly1' not defined in LVS file

quitting.

Forking: /CMC/tools/cadence/ASSURA-613.03.20.022.linux/tools/assura/bin/32bit/capgen -substrate_stamping_off -techdir /autofs/fs1.ece/fs1.vrg.CMC/kits/amsp35.v4.00/assura/h35b4/h35b4d3/RCX-typical -lvs /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/ASSURA_LVS/rail_comparator/rail_comparator.xcn -p2lvs /autofs/fs1.ece/fs1.vrg.CMC/kits/amsp35.v4.00/assura/h35b4/h35b4d3/RCX-typical/p2lvsfile -length_units meters -cap_unit 1.0 -selected_paths_proper -p poly1,capgen_gate,diffusion -no_cap_correction -cap_ground_layer net_psub -dsub net_pwell,net_nwell,net_psub -lexclude poly2,poly1 -blocking cblock_met3_poly1,met3,met2,met1,poly2,poly1 -blocking cblock_met3_psub,met3,met2,met1,poly2,poly1,diffusion,fox -blocking cblock_met2cap_met2,met2cap,met2 -blocking cblock_met1_poly1,met1,poly1 -blocking cblock_poly2_poly1,poly2,poly1 -blocking cblock_poly1_psub,poly1,diffusion,fox -res_blocking rblock_poly1,net_poly1 -res_blocking rblock_poly2,net_poly2 -res_blocking rblock_met1,net_met1 -res_blocking rblock_met2,net_met2 -res_blocking rblock_met3,net_met3 -res_blocking rblock_met4,net_met4 -sw3d /autofs/fs1.ece/fs1.eecg.roman/yuhu/AMSP35HV/ASSURA_LVS/rail_comparator/rail_comparator

*WARNING* Bad return status from RCX script generator. 0x100

How to solve it? Thanks!

↧

Changing bBox of cell using dbTransformBBox/geTransformUserBBox

August 22, 2014, 8:46 am

≫ Next: bus value export to table

≪ Previous: Problem with Assura license

Hi,

I am trying to reduce the bBox of my cell (it has been enlarged and is much larger than my prBoundary) and I have tried the following commands:

cv_layout = dbOpenCellViewByType("lib" "cell" "layout_test" "maskLayout" "a")
transform = list(list(-10000 -10000) "R0" 1)
dbTransformBBox(cv_layout~>bBox transform)

When I go back and check cv_layout~>bBox, nothing has changed. Am I missing a step? Or is there a different way to change the bBox of an entire cell?

Thanks,
Elizabeth

↧

bus value export to table

August 22, 2014, 11:14 am

≫ Next: Viewing Monte Carlo results having run spectre and viva standalone

≪ Previous: Changing bBox of cell using dbTransformBBox/geTransformUserBBox

I am working on an ADC. I would like to be able to export the value of the output bus to a table. Basically I have an n-bit hexadecimal bus and a trigger signal. I am using Visualization & Analysis XL.

I would like to have a table on the screen or a file that reports the value of the bus on the falling edges of the signal. I have read the documentation.

Even in Silvaco Smartview you can step through falling edges & look at the value of a bus. I can't believe that Cadence can't do this but I can't see how with the calculator. What have I overlooked?

↧

Viewing Monte Carlo results having run spectre and viva standalone

August 22, 2014, 11:15 am

≫ Next: How to create pad for SMD parts

≪ Previous: bus value export to table

I have run montecarlo in spectre (13.1) standalone (from a netlist). Then I attempted to view the results in viva (6.1.6) also standalone. Viva sees the nominal and last iteration for all signals but not the other iterations (20 total). All of the expected montecarlo files appear to be in the .raw directory as PSF, etc files. Is there a means to view the entire set of results? Should I be able to see all outputs or only the voltage on one net that was exported via a export netx = oceanEval(...) statement?

The DC simulation consisted of 20 montecarlo runs with a 10 step temp variation within:

mc1 montecarlo saveprocessparams=yes variations=all numruns=20 scalarfile="mc_results.dat"{
   swp sweep param=temp start=-55 stop=125 step=10 {
     oppoint dc oppoint=logfile
     export vptat = oceanEval(" v(\"net30\" ?result 'dc ) ")
}
}

↧