Hi,
I am trying to reduce the bBox of my cell (it has been enlarged and is much larger than my prBoundary) and I have tried the following commands:
cv_layout = dbOpenCellViewByType("lib" "cell" "layout_test" "maskLayout" "a")
transform = list(list(-10000 -10000) "R0" 1)
dbTransformBBox(cv_layout~>bBox transform)
When I go back and check cv_layout~>bBox, nothing has changed. Am I missing a step? Or is there a different way to change the bBox of an entire cell?
Thanks,
Elizabeth
↧
Changing bBox of cell using dbTransformBBox/geTransformUserBBox
↧
Regarding RFlib in cadence 615
Dear Team,
I was using cadence 514 and just now switch to cadence615. I have included RFlib from " ../ic5p41/tools/dfII/samples/artist/rfLib "
But i can not able to find for cadence 6. Can you please provide me path to include RFlib.
Regards,
Darshak
↧
↧
Error on creating wire in Virtuoso
Hi,
When i'm trying to create a wire in Schematic editor of cadence Virtuoso
i'm getting the following error and wire is not getting created.
I'm able to copy/move/extent the already existing wires though..
"Loading layers.cxt
* Field is "color" *
*Error* hiCreateCyclicField: value must be contained within the list of choices"
It was working fine till yesterday.
If anyone know the solution/fix for this problem, please let me know..
reagrds,
Shameel
↧
How can i make a ring(donut) void in allegro pcb editor.
Hi!
I want to create a crosshatched circular shape, with a woid in its center and an other few mm woid not far from the outer ring. Its like a ring shape in an a bigger ring shape. How can i make it, or can i make it at all in allegro?Somelike i attached.
↧
Propagation Delay OrCAD PCB Editor 16.6
Is it possible to get a net propagation delay report in OrCAD PCB Editor 16.6 ?
It appears as though a net constraint for propagation delay can be set but is there a way to determine an existing nets propagation delay?
Thanks in advance for your help.
↧
↧
Redefine a library from SKILL?
I work in CAD support, so I find myself doing this a lot in cds.lib:
UNDEFINE someLib
DEFINE someLib /some/users/workarea/someLib
I was wondering if this can be done from SKILL without actually editing cds.lib. E.g.,
ddUndefineLib("someLib")
ddCreateLib("someLib" "/some/users/workarea/someLib")
N.B. ddUndefineLib does not exist, and editing lib->readPath doesn't seem like it would work.
↧
Generate OrCAD Netlist and BOM from Command Line
I'm trying to generate a netlist and BOM from a given OrCAD DSN from the command line (for integration within my version control).
For netlist generation I found (from searching the forums) pstswp.exe. Unfortunately I couldn't find any documentation on this, and it doesn't give any help information from the command line. I'd like to generate a netlist with the orPads2k.dll (as if from the 'other' tab in OrCAD) using pstswp.exe, is this possible? If not is there another way to automate this, using that dll?
For BOM generation I found a few Tcl scripts that generate BOMs.Is there any way to run these scripts without having OrCAD open, from the command line?
Ideally I'd like to generate these two files automatically from the command line at any time, given a DSN.
Thanks!
↧
Simulating basic Log Amplifier and Antilog Amplifier using diode as well as transistor
I'm learning the basics of Cadence OrCAD 16.6 Lite. I want to design and simulate the basic Log Amplifier and Antilog Amplifier circuits both using diode as well as transistor. I'm able to design these circuits. What values should be provided to the diode and transistor? In order to verify the simulation output, I have to calculate the output voltage theoretically, which needs the values of saturation currents for the diode and transistor. How to find these values? I have used the component DIODE from DISCRETE library and NPN BCE from TRANSISTOR library. Also tell me if I have chosen the correct components or not.
↧
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↧
↧
How to change Ref. designator size
hai all,
I am user of Orcad PCB editor 16.0. while setting Ref. designator i found its size is too big. I am not able to place near comp. due to high density and the Ref. Des. size is too big. If I make down the size I can fit them in position. I tried to change by selecting all text only and then Setup> Design parameter> Text option. But I am not getting Apply button highlighted. so nothing is changing on the board. Pl s let me know how to change the text size of designator in design.
regards,
↧
Missing Ref Des, or invisible
I have a board with several components where someone had either deleted that components ref des, or made it invisible somehow. How can I get the parts ref des back visible on the silkscreen?
Thanks
↧
Convert *.sch from old version of OrCAD
Hello all!
I have found a lot of sch. files, made in very old version of OrCAD - v1.25 (1985-1987 years). Also I have this version OrCAD with all libraries, and all work fine under DosBox emulator. I have two question:
1) Is it possible to convert from sch OrCAD v1.25 into any other modern file format?
2) I can write my own file convertor if will know the structure of .sch and .lib files in OrCAD v1.25. May be possible found somewere this information?
↧
4 Layer PCB First Time
Hi Guys,
I am new to both OrCAD/Allegro and 4 Layer PCB's. I'm having a tough time using the Spectra auto router to properly place via's in my design. Do I need to make and specify special via's when creating a multilayer board. I looked in costraint manager, and the default via doesnt quite look right.
Any advice would be great - Thanks so much!
↧
↧
E- Can't find window; form.nc_drill
HiAll,
Here i have attached skill code for scripting(automatic drill generation).
while loading skill i got below errors
E- Can't find window; form.nc_drill
E- Can't find window; form.nc_parameters
Any one please help me out.
Thanks,
Karthik.
↧
bare die on pcb
Hello,
I have a question similar to the one posed in http://www.cadence.com/Community/forums/t/20786.aspx .
In my design I will have bare silicon chips directly mounted on the pcb (flex pcb) in a rather complex 3d setup. Those chips have wirebond pads which will be naturally connected by wirebonds to the corresponding pads on the flex. What is the best way to proceed? From what I have found, I suppose I have to create a new part in the part designer with a completely self drawn footprint for each chip and to define the wirebond pads together with a wirebond layer in their padstacks? I searched through the documentation but did not find anything resembling exactly this situation. I would be grateful if someone could point me to an appropriate example.
Thank you very much.
↧
Configuring new PDK
I was configuring the new PDK in Cadence virtuoso version IC6.1.4.500.12( one PDK is already existing in the home directory). so i make a new folder(named "new_PDK") in the home directory and added the files(cadence.cshrc, cds.lib, .cdsinit, .cdsenv, bindkeys and the PDK folder). when i source the cadence.cshrc file from from folder new_PDK, i am listing out the problems i am facing:
1. its shows techfile conflict
" there is a conflict in techfile graph
Look at techfile reported error massage in CIW
correct techfile conflict before proceeding "
Whill loading the files, it takes techfile.tf, pdkutil and display.drf file from PDK folder olny.
2. In the schematic window, i can call the instances but unable to connect using wires(wires are not coming. rest all shortcut keys are working.
3. In the layer selection windows(LSW) palletes are not visible.
" (LE-101804): Cannot get valid layer form LSW window. "
i can see the layer when i click on layer but again shows blank when i scroll it down.
4. Cadence windows crash when i try to make any layer in the layout.
" \o (LE-101804): Cannot get valid layer form LSW window.
\a leSetLSWBBox(list(57:328 207:1028)) "
Everthing working properly with the old PDK exist in home directory.
Please help me out.
↧
rodAlign a pcell in layout out of gird
Hello everyone,
I use cmd: rodAlign to place a pcell(AA) in a layout, as:
cellId=dbOpenCellViewByType("testLib" "testCell" "layout" "maskLayout" "w")
instId=dbCreateParamInstByMasterName(cellId pdkName inst "layout" "inst_1" 0:0 "R0" 1)
rodAlign(
?alignObj rodGetObj("inst_1" cellId)
?alignHandle 'lowerLeft
?refPoint list(0 0) )
And the pcell(AA) is out of gird(0.005u), but if I use bindKey "i" to place this pcell in layout, it's no out if gird.
I found that the refer point of cmd:rodAlign is the lowerLeft of the pcell, but the refer point of bindKey "i" is the origin in the pcell. And i think it maybe the reason.
Who can help me to work out this problem?
Thank you very much!
Lee
↧
↧
PSpice Simulation errors
hello everyone,
I'm trying to simulate a huge schematic with a plenty of hierarchical blocks. In fact, i have had a lot of errors . I tired to replace all spaces by undescore but there was no results!
Can you help me please ?
Sincerly,
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1903153.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1903153.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948829.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948829.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948753.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949425.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949283.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949337.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949357.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949263.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948785.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948821.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949247.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949263.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949283.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949227.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948785.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949337.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949413.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948821.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949357.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948645.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949247.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949227.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949425.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948645.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1949413.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948753.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948583.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_rendement_N1948583.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833670.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833582.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902595.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833670.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833670.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833582.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Soft_start_N1833390.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902651.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902671.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902595.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Lim_0A8_N1823030.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902495.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Lim_0A8_N1822978.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Lim_0A8_N1822978.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Lim_0A8_N1822978.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_Lim_0A8_N1823030.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902531.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902851.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902851.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902495.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902851.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902465.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902651.
WARNING(ORNET-1043): Illegal net name step_down_5_24 _to_3V3_N1902851.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_PS _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Total number of: PARTS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: OFF PAGE CONNECTORS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: BOOKMARKS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: COMMENT TEXT for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: NETS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: HIER PORTS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: DRCS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: TITLEBLOCKS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: POWER SYMBOLS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: HIER PINS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: PARTS PINS(Logical) for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: SINGLE NODE NETS for: 'N1948785' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Total number of: PARTS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: OFF PAGE CONNECTORS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: BOOKMARKS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: COMMENT TEXT for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: NETS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: HIER PORTS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: DRCS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: TITLEBLOCKS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: POWER SYMBOLS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: HIER PINS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: PARTS PINS(Logical) for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Total number of: SINGLE NODE NETS for: 'step_down_5_24 _to_3V3' [ in PAGE: , Mode: Inst, MatchCase: No, DESIGN: C:\USERS\SESA255220\DESKTOP\NX_SIMULATION_VF_27_08_2014\ARCHI_NX_SIM_VF.DSN ] : 0
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(3.70, 0.80)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(6.40, 1.00)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(8.60, 3.50)
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(5.50, 1.80)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(5.20, 3.30)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(3.40, 3.00)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(3.70, 3.80)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(5.20, 5.20)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(3.30, 4.90)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(3.10, 5.60)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(6.70, 2.50)
--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(7.70, 2.50)
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569733.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N25696651.
WARNING(ORNET-1043): Illegal net name ULP_ps _N2569609.
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
Creating PSpice Netlist
INFO(ORNET-1041): Writing PSpice Flat Netlist c:\users\sesa255220\desktop\nx_simulation_vf_27_08_2014\archi_nx_sim_vf-PSpiceFiles\SCHEMATIC1\SCHEMATIC1.net
INFO(ORNET-1156): PSpice netlist generation complete
↧
Cadence Allegro Menu customization
Hi Friends,
Is it possible to add a text file or Excel sheet in the Allegro PCB editor menus.So that file will be open once mouse click is done.I have added the menus by editing env file but am not aware how to link the specific files to the menu command.
Looking for valuable comments.
Thanks and Regards
Praveenkumar Ravi
↧
Setting up used defined graph properties
Dear Team,
I am facing too much problem for setting up graph properites again and again like font size, background color, marker fonts etc.
Can you please guide me how can i permenantly configure my default graph setting so that it will not change for every graph.
I am using cadence 6.1.5
Please answers my doubts. I am posting many post but not getting answer. Otherwise provide your customer care email. Why cadence is not that much userfriendly.
Regards,
Darshak
↧