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abutment and controlling S/D dropping

April 16, 2014, 7:05 am
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I am an end user layout engineer. I am not a developer of PDKs or Pcells, etc. so I am at the mercy of what is given me to use for the most part. I do develop SKILL code for automation of the layout task. One of the problems we encounter is when we abut pcell mos devices and the source/drain of one of the abuted devices drops off. That is all fine except sometimes when you pull the devices back apart the source/drain does not come back. This is a problem and probably has something to do with the way the pcell was created. If I happen to instantiate any new pcells of the same type the source/drain will also be missing on the new device as well. 

As an end user in most libraries I found that if I view the properties of the pcell most our libraries have a 'disable callback' button I can click on, apply the form, then click off and re-apply the form and the source/drain comes back and all is well.

My issue is that I am developing some Skill code that copies a selected pcell into another view, flattens it and extracts data but I need the source/drain to always be there so I can extract data off the shapes. Is there a way I can trigger this new view copy to get the source/drains back? Is there a Cadence functional way to maybe disable and re-enable calbacks to it to maybe do with Skill code what I do manually? I've been looking and can't seem to find an answer.

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Netlist error when using Global Sources in hierarchy editor

March 29, 2014, 1:00 pm
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This happens when I try to use global source in post layout simulations.

The circuit under test is designed with a global source. And I believe the pin names are vdd!/gnd! because I have passed the LVS successfully. But when I try to use hierarchy editor to do the post-layout simulation, it goes wrong. If I compile the schematic view of the circuit with its test circuit, it works well and I get the right simulation result. But if I compile the extracted view of it, it turns out to be wrong. So I check the netlist of it and find that it automatically changed the global source vdd!/gnd! to _net0/_net1. I think it may recognize the two vdd!/gnd! in extracted view of circuit under test and schematic view of test circuit to be a violation of same name and changed it automatically. But they are definitely the same. They are the global sources.

Do you guys know whether there are any settings to fix this? I have looked into many tutorial and they do the post-layout simulation right the same way with no problem. So I think there may be some basic setting errors in my environment. By the way, I’m using IC 5.1.41

 

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Choose grid properties

April 27, 2014, 10:11 am
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I open Setup>Grid in PCB Editor. How can I choose all these Offsets and Spacings ? 

Bring textbooks and manuals for students.Thank you.
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StrongGroup suffix in net name

April 25, 2014, 6:33 am
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When I use VXL and gen from source, the transistor generated have weird net name assigned to its source/drain terminals. Rather than named "n1", the net name on the inst term is appended with "_StrongGroup_#" e.g. "n1_StrongGroup_1".

FYI in the schematic I have nfet with m=16, source tied to n2, drain tied to n1. After gen from source, the nfet in layout has source term assigned to net n2, but drain term for each transistor is different: n1_StrongGroup_1, n1_StrongGroup_2, ..., n1_StrongGroup_16.

I would like to know under what circumstances would this happen, what's the purpose of these "StrongGroup" and how to deal with these weird nets. To get back the "parent" net, I could potentially do "car(net->signals)". Still, it is confusing because a net is no longer a simple net and we might need addtional queries to get back the actual net without the StrongGroup suffix.

Tried to look for documentation for this but couldn't find anything.

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[ADE L/XL] Setting a skill expression to a design variable

April 28, 2014, 9:08 am
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Hi All,

I couldn't find any post on this topic, and hope my next question makes sense...

I have a testbench simulating both a 'tran' and a 'pss' analysis. I'd like to disable automatically some vpwl sources (related to the transient Power-down control) when doing a pss/pnoise.
Henceforth, I wanted to create a variable to set all the values in the vpwl to 0 when the PSS is detected (so that the PSS detects only the clock).
Basically, I wanted to have my "pss_off" variable set to either 1 or 0 in this fashion:

if(pcreMatchList("pss" asiGetEnabledAnalysisList(asiGetSession(hiGetCurrentWindow()))~>name) then 0 else 1)

But this format is not accepted for netlisting (although the calculator doesn't complain). I've tried to format it to a string but as unsuccessfully.
Is there a smart way to push a skill expression into the 'Value' field of an ADE L/XL design variable?
Maybe I'm doing it wrong, there might be another type of sources than vpwl which can be enabled on tran and disabled on PSS...

Thanks in advance,
Best regards,
Matth

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Cannot find nom.lib

April 28, 2014, 10:43 am
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Hello. I have the Pspice 9.1 Student Version and i copied some pspice files into my USB stick. From that point after, i have been getting this error message "Cannot find nom.lib". I have tried adding nom.lib in the' Library and Include Files 'option under the ' Analysis ' tab in the 'Schematic' Editor but i still get this message. Can someone help solve this?

Thank you. 

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Parametric analysis - voltage error in the netlist

April 28, 2014, 2:04 am
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I found that when I run parametric sweep with fine voltage step, netlists are sometimes generated with wrong value. For example, when I run parametric analysis with the voltage changing from 0 to 1V with 1/2560V(=390.625uV) step, 62.5mV is changed to 62.4999999999998V in the netlist. 

Is there some kind of precision issue during parametric sweep? Is there a way to fix this? I am currrently using ic-6.1.5.-64b.500.9

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could not launch skillDev IDE

April 23, 2014, 1:48 pm
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Hi, there.

I'm currently using IC6.16.

I tried to invoke skillDev IDE from the CIW window and the only message I got 
was:
Loading skillDev.cxt

but nothing happened after that.

I looked at the CDS.log and here it is

\# Program start time UTC 2014.04.23 10:25:12.230
\# Local time Wednesday 23 April 2014, 10:25 am
\o Program:@(#)$CDS: virtuoso version 6.1.6-64b 05/03/2013 14:44 (sjfnl178) $
\o Hierarchy:/usr/local/cad/cadence/ic6/ic616005/tools.lnx86/dfII/
\o Sub version:sub-version  IC6.1.6-64b.101  (64-bit addresses)
\# Host name (type):Jupiter.Klipsch (x86_64)
\# Operating system:Linux 3.11.10-7-desktop #1 SMP PREEMPT Mon Feb 3 09:41:24 UTC 2014 (750023e)
\# Linux /etc/issue:Welcome to openSUSE 13.1 "Bottle" - Kernel \r (\l).
\# X display name (WxH)::0 (1920x1206)
\# Available geometry:TL(0:6) BR(1919:1205)
\# X server:The X.Org Foundation
\# Depth of Visual (Root):24 (24)
\# Number of Planes Used:24
\# X version:11.0 (vendor release 11403901)
\# X resource pool:base 0x5000000, mask 0x1fffff (2097151), shift 0
\# current id 0x0, current max 0x1ffffa (2097146)
\# Max data seg size:    unlimited
\# Max process size:    unlimited
\# Initial sbrk value:       303 MB
\# Available memory:    13,728 MB
\# System memory:    16,089 MB
\# Maximum memory size:    15,844 MB
\# Max mem available:    13,786 MB
\# Initial memory used:        58 MB
\#        process size:       687 MB
\# Qt version:4.7.2
\# Window Manager:kde
\# User Name:nkerstram
\o Working Directory:Jupiter.Klipsch:/home/nkerstram/projects/cadence
\# Process Id:5738
\o 
\o COPYRIGHT © 1992-2013  CADENCE DESIGN SYSTEMS INC.  ALL RIGHTS RESERVED.
\o           © 1992-2013  UNIX SYSTEMS Laboratories INC.,
\o                          Reproduced with permission.
\o 
\o This Cadence Design Systems program and online documentation are
\o proprietary/confidential information and may be disclosed/used only
\o as authorized in a license agreement controlling such use and disclosure.
\o 
\o           RESTRICTED RIGHTS NOTICE (SHORT FORM)
\o Use/reproduction/disclosure is subject to restriction
\o set forth at FAR 1252.227-19 or its equivalent.
\# Available memory:         13,714 MB at UTC 2014.04.23 10:25:12.580
\# Memory report: Maximum memory size now 13,787 MB at UTC 2014.04.23 10:25:12.580
\o Loading geView.cxt 
\o Loading menuBuilder.cxt 
\o Loading schView.cxt 
\o Loading selectSv.cxt 
\o Loading LVS.cxt 
\o Loading layerProc.cxt 
\o Loading pte2.cxt 
\o Loading xlUI.cxt 
\o Loading auCore.cxt 
\o Loading dcm.cxt 
\o Loading vhdl.cxt 
\o Loading seismic.cxt 
\o Loading ci.cxt 
\o Loading ams.cxt 
\o Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.01s.
\o Loading oasis.cxt 
\o Loading analog.cxt 
\o Loading asimenv.cxt 
\o Loading spectrei.cxt 
\# Memory report: using         160 MB, process size 813 MB at UTC 2014.04.23 10:25:13.713
\o Loading relXpert.cxt 
\o Loading awv.cxt 
\o 
\o 
\a _ilgRunSkillIde()
\o Loading skillDev.cxt 
\r nil

When I looked at the Options->License, I have license #s 111, 95115 and 95220 as 
Checked Out Licenses and # 900 as Relevant Licenses.

I would appreciate if someone could help me.

Many thanks in advance.

Best regards,

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K Stability factor

April 28, 2014, 9:27 am
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Hi 

I use SP analysis in ADE L and draw the KF (stability factor).

The result is different compared to the K factor derived from any known equations (I got the equations from Pozar's book). i.e. I use for example, the Yij parameters and use my own equations for K.

How I can get more information about how KF in SP analysis is calculated in ADE L ? 

 

Thanks,

Hamid 

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Bulk connection of the mos

April 10, 2014, 8:55 pm
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Hi 

 I'm working for rewriting the mos bulk connection but I'm not getting how to get only bulk connection information 

I tried this command geGetEditCellView()~>sigNames..By this I'm getting all pins info also

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Unplaced/Placed symbol;s in PCB EDITOR

April 28, 2014, 6:19 am
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I have loaded an netlist in the PCB editor and since the symbols are not placed I cannot see any of the symbols. I know they are there since Place/Manual shows all the reference designators. Why can't I see the symbols ?

 

I then used Quickplace and all the symbols are located on the right side of the board. I want to be able to select certain reference designators to group the symbols. When I goto Manual Place there are now no reference designators. How do you select a group of reference designators ? 

 

Is there anything that explains the differentces between unplaced and placed symbols ?

 

TIA Lenny 

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Virtuoso Editor Tools Menu

April 28, 2014, 12:13 pm
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When I first click on the "Tools" menu in the Virtuoso Schematic/Layout editor the entire Cadence GUI freezes for up to 30 seconds. This does not happen on any subsequent times I click on the Tools menu, even from different windows.

My guess is that it tries to find what tools are available and build that menu on the fly. If that is correct, there should be a way to cache that information once as oppossed to doing the search every time Cadence is restarted.

Any suggestions are appreciated.

 

--Tavi

 

PS. I'm using the latest hotfix release of IC5141

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Kitchens Cabinets London

April 29, 2014, 7:01 am
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Normal 0 false false false IN X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin-top:0cm; mso-para-margin-right:0cm; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

Kitchens Cabinets London, Thirty Ex Display Kitchens To Clear. www.exdisplaykitchens1.co.uk£ 595 Each with appliances.

 

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Modifying an extracted view for post layout simulation.

February 20, 2012, 8:31 pm
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I am using IC 5.1.41 and Calibre 2010.4. I have an extracted view which is extracted by Calibre and I want to use it for post-layout simulation. When I modify the extracted view, Analog environment gives the following error:

ERROR: Netlister: the cellview **** was modified since last extraction.

Is there any way to modify an extracted view and use it for post layout simulation?

Thank you very much.
 

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Assura Layout extract.rul debug

April 10, 2014, 1:04 am
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I am writing extract.rul for a IC technology and I am a beginner.

Is there a simple way to debug while running the extraction, i.e. the visualization of the resulting layers from geomAnd and geomAndnot  operations?

Thanks,

 

Pietro

 

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Abstract Generator : abstract view with just "M1 net layer" => instead of "M1 drawing" and "M1 pin layers"

April 29, 2014, 5:57 am
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Hi !!

I managed to get an Abstract view of my simple inverter cell, from a layout.oa view (up to M1 layer). See attachment.

However, in this Abstract view, i just have one layer : M1 net. Actually I would like to have "M1 drawing" and "M1 pin" layers + the contact "CO layer" to see the pins (vdd/vss/A/Y) in the viewer and the contacts.

In my layout.oa input file, my strategy for the pin definition is:  

one layer or M1 drawing with connectivity vdd

+ layer pin M1 on this layer (Terminal Name : vdd)

+ layer text drawing "vdd" (no connectivity) 

 

I think, I have to do something "Step Extract" at Signal & Power panels but I cannot do what I want. I tried different combination with no sucess.

 

Thanks for any help !!

 

P. 

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frames around PCB?

April 25, 2014, 5:50 pm
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I do drawings of 0.5" PCBs and some 12" PCBs.  I want a frame with instructions.

Regardless of PCB size, I want the PCB image to mostlly fill the frame.  I've been importing different sized DXFs.Is there a better way?

Can I make a frame that is somehow changeable in size that I can just wrap around my PCB drawing?

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How can I preserve designators from changes?

November 24, 2013, 6:41 pm
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Hi
In the Orcad capture schematic environment when we try to copy a page in a project file and paste it into an another project all designators automatically changes.
How can I preserve them from changes?
It is important to me to save all designators without changes.
Thanks a lot

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Extracting generic devices with Assura

April 29, 2014, 7:54 am
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I would like to extract my own two terminals device from the layout.

The first terminal is derived with specific derivation rules, the second terminal instead should be named according to the layout x,y coordinates of the first terminal.

Example:

 XavD2_1 avC1 prefix_x_y DEV

avC1_x_y is a given prefix followed by the first terminal layout coordinates

Is this possible?

Thanks,

Pietro

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How to Place Components without Dimension Information

April 29, 2014, 10:53 am
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Hello all,

I'm having difficulty locating the function that will allow me to place components without dimension information about the footprint. This wouldn't be a problem if my computer isn't so slow and I didn't have 150~ parts in my design. My computer will often freeze when PCB Editor decides to display footprint dimensions for every 0805 resistors / capacitors or soic8 ICs.

Thank you for your time,

Andy Park 

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