Hi,

   I am unable to to create a coverpoint using with it is giving an error . My code is as

   cp_in1 : coverpoint in1 {

        bins b1[ = in1 with ($countones(item) == 3);

   }

  Here in1 is a 8-bit variable. I am using INCISIV 13.10.013.

  So please tell me how do i create the point for this.

Thanks

Srikanth M.

Hi,

I want to get a list of pins names and which direction the pins have from a symbol/schematic. I guess SKILL is the way to go? I new to SKILL, so if someone could push me in the right direction I would be grateful:)

Hi,

Seems I had a design rejected from the board house because I was missing the board outline on my artwork. So I checked it out and it was only on the bottom etch layer.

Apparently they need the outline on each layer.

 Using allegro 16.5, I went to the artwork window and saw that the subclass board geometry/ outline was missing on ALL of the films, even the bottom one. So I added it to all layers, including the mask and silk layers.

I also checked the photoplot outline. It's present and larger than the board itself by about 1/2".

I cannot change the width of the outline. It's zero.

I even futzed with the undefined line width and shape bounding box and no dice, still no outline except on the bottom etch layer.

Can someone give me a hand here? I am not an expert here but I have a ton of designs to get out stat, since I am the only one left here.

Thanks in advance

Hi All,

I'm running 16.6-S026 on a Win 7 64 bit laptop.

For the past few days I've been unable to get into Part Developer. I open the project manager and open a schematic. 

Click Tools > Library Tools > Part Developer. The Part Developer splash screen comes up, but the Part Developer never opens. 

No errors, no messages, it just freezes. I can still use the rest of the laptop. It's just the Part Developer that stops responding.

I have to End Task. Has this happened to anyone else?

Thanks!

Bob 

Hi,

I am trying to run Monte Carlo analysis using ADE with TSMC 65nm kit. I tried the mismatch analysis and it works.

The problem happens when I try to run the process analysis. When I define mc_xxx sections in the model libraries and run the simulation, I always get errors about parameters that are redefined. Any idea about that?

Thanks, 

Hi,

I have 200 DACs and buffer opamps in my design. Is there a way to create a schematic/netlist in Capture CIS without copying one by one all the sub units.

    I have a circuit with serveral transistors and wish to perform backward transient simulation, i.e., for a given final condition for each node, wish to guess/calculte the initial node voltage. Seems that in cadence transient simulation setup it doesn't allow the inital time to be less than the final time. So I'm wondering  anybody know how to do this? Thank you very much.

hi,everyone,

I am simulate a crystal osc ,which main circuit is just a simple nmos with it's drain connected to gate through a resistor.And I put a zero vdc at the drain to do stb analysis.It's oscillate frequency is  25M ,so i choose frequency from 24M to 26M ,linear step ,every step is 100.

But i found the result is different in ADE-L and ADE-XL.Accroding to the waveform,the results in ADE-XL in right

i don't know which one i should trust.My cadence version is IC 6.15 and each case i use spectre to simulate.spectre version is 7.2

thanks any help in advance

i would like to have a custom metal fill pcell that will have poly, m1, mt and am and would like to have them either on or off. size of the rectangle fill is 12x12 um.

i know there's already a fill cell but the size of the rectangle is too small. 

My script has some print outs and is there a way to create a print out log GUI of those print outs.

The closest thing I could find is the  hiCreateMLTextField, but I would have to append every string to the current value. Also, I dont know how clear it may become in reading previous and if the string would become too big and cause problems.

It is not that big of an issue to append the string, just looking for the most effective way to have a print out log GUI.

The print out would be strictly used for reading print output. I know I can print to the CIW, but some users want a print out GUI.

Paul

Looking for documentation cnnot find anything about this in FETXTCMDREF.....where should I look to find everything about clock tree synthesis including the Azuro features

 Hello all,

I have the following issue: I am trying to run an ocean script (diffopamp.ocn) inside an interactive session in a linux shell.

The ocean script diffopamp.ocn have the lines:

load("skillafv.il")

AFVtestInit( "./SPECS/CmirDiffAmp4.spec")

 And the script skillafv.il has the procedure:

procedure(AFVtestInit(file "t")
let((ps line key (fp infile(file)) (count 0))
AnalogTests = ’unbound
AnalogTests = makeTable(’AnalogTests nil)
if(fp then
while((line=lineread(fp))
println(line)
count++
;;AnalogTests is equivilent to a record which is indexed on a key
;; that contains a value and two other fields, pass and fail
;; value@keyslot pass fail
ps = line
when(length(ps) < 3
printf("Field formats are:\n testkey m value\n testkey x value\n
testkey r lowerLimit upperLimit\n")
printf("Where testkey is the name of the test.\n character m means
minimum value\n character x means maximum value\n character r means range of
2 values\n")
error("Test specification requires THREE or more fields; line %d\n
contains %s\n"
count line)
)
key = get_pname(car(ps))
AnalogTests[key] = tconc(AnalogTests[key] get_pname(cadr(ps)))
AnalogTests[key] = lconc(AnalogTests[key] cddr(ps))
AnalogTests[key] = lconc(AnalogTests[key] list(0))
AnalogTests[key] = lconc(AnalogTests[key] list(0))
AnalogTests[key] = lconc(AnalogTests[key] list(0))
;;this gets the tconc formatted list and stuffs it in the table
AnalogTests[key] = car(AnalogTests[key])
)
else
error("Cannot OPEN file %s \n" file)
)
)
)

 When I load the ocean script inside the CIW session using: load("diffopamp.ocn") there are no issues, and I can execute the procedure inside the skill script. But when I tried to use an interactive session called in a unix shell, and after typing:

ocean>load("diffopamp.ocn")

 I got the error:

*Error* eval: unbound variable - AnalogTests

Can somebody please help me? 

Best Regards,

Angel

Hello,

Could we use the transient analysis results as a stabilization point (tstab) for PSS analysis? If so, how could we acheive it? Is there any documentation on this? Any inputs will be helpful.

Prakash.

Hi all,

i've designed a full adder circuit in cadence virtuoso. i wanted to know how to calculate over all delay. i know how to calculate delay between two signals using calculator tool. But dont know to calculate over all delay. Please help.. . 

14 hours and I couldn't figure out where the problem really is.

Somehow I cannot go past convergence error for my DNL-INL test model (attached the verilog-a behavorial model file).

  Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 7.0.1.179.isr16 -- 15 Jan 2009
Copyright (C) 1989-2007 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

Simulating `input.scs' on eecad29.engr.sjsu.edu at 11:59:39 PM, Sat Apr 26, 2014 (process id: 9033).
Command line:
    /apps/cadence/MMSIM0701179/tools.lnx86/spectre/bin/32bit/spectre  \
        input.scs +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre2_22708_13 -format sst2 -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 9033

Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Using new Spectre Parser.
Auto-loading AHDL component.
Finished loading AHDL component in 0 s (elapsed).
Installed AHDL simulation interface.
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ (775)
Compiling ahdlcmi module library.

Warning from spectre during circuit read-in.
    WARNING (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

Could not open ahdlcmi module library input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so
        input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so: cannot open shared object file: No such file or directory
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ (775)
Compiling ahdlcmi module library.

Warning from spectre during circuit read-in.
    WARNING (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

Could not open ahdlcmi module library input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so
        input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so: cannot open shared object file: No such file or directory

Circuit inventory:
              nodes 10
     adc_8bit_ideal 1    
            DNLpart 1    
            vsource 2    

Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre2_22708_13, ).

************************************************
Transient Analysis `tran': time = (0 s -> 10 ns)
************************************************

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.

Trying `homotopy = gmin' for initial conditions.

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.

Trying `homotopy = source' for initial conditions.

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.

Trying `homotopy = dptran' for initial conditions.

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.

Trying `homotopy = ptran' for initial conditions.

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12:  Array access out of bounds near line number 31. Correct the problem and try again.

Trying `homotopy = arclength' for initial conditions.
None of the instantiated devices support arclength homotopy. Skipping.

Error found by spectre during IC analysis, during transient analysis `tran'.
    ERROR (SPECTRE-16080): No DC solution found (no convergence). 

The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.
            Failed test: | Value | > RelTol*Ref + AbsTol


The following set of suggestions might help you avoid convergence difficulties.  Once you have a solution, write it to a nodeset file using the `write' parameter and read it back in on subsequent simulations using the `readns' parameter.

 1. Evaluate and resolve any notice, warning, or error messages.
 2. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings.  Print the minimum and maximum parameter value using the `info' analysis.  Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

 3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

 4.  Enable diagnostic messages by setting option `diagnose=yes'.
 5. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
 6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file and set as many nodes as possible.
 7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
 8. If simulating a bipolar analog circuit, ensure the region parameter on all transistors and diodes is set correctly.
 9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Increase the value of gmin (on options statement).
11. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to somewhere in the range of 0.1 to 0.5 using `pivrel' (on options statement).
12. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.
13. Divide the circuit into smaller pieces and simulate them individually, but ensure that the results will be close to what they would be if you had simulated the whole circuit.  Use the results to generate nodesets for the whole circuit.
14. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run the transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when all of the signals in the circuit are not changing) and write the final point to a nodeset file. To make the transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach will fail or be very slow because the circuit contains an oscillator.  Often times the oscillation can be eliminated for the sake of finding the dc solution by setting the minimum capacitance from each node to ground (`cmin') to a large value.

Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.

Error found by spectre during DC analysis, during info `finalTimeOP'.
    ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.

Analysis `finalTimeOP' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.

Hi everyone,

    I'm having a trouble creating a new project using the programmable logic wizard in OrCAD Capture. The vendor and family list is empty so I can't create a new project. How to fix this issue? Please help me as I'm fairly new to this software.

Thanks.  

how to add library gpdk180 into cadence virtuoso IC615  ??

thanks 

 Is there a way in spectre of AMS-designer to debug current flow?   Currently I'm using AMS interactive with simvision to debug from the top level.  If I see an unexpected current value from a top port, I would like to follow down the hierarchy to see what the major contributor up the hierarchy.  Are there any ways to do this?  Currently I pause the simvision, probe port flows down the hierarchy.  It's a bit cumbersome and I'd like to see a way to do it more elegantly. Thanks!