Hi!
I have to you the following questions:
1) How do I define the new VIA so that I can use it later in Allegro? I know that I have to use the PAD Designer, but where I have to save the designed VIA so it is later visible in "Edit VIA List" within Constraint Manager in Allegro?
2) How I add to the layout a single VIA e.g. if I want to connect two planes together that are on different layers?
Best regards,
Krzysztof Sielewicz
Hi All,
Can I know how to generate waive DRCs report using skill?
Thanks,
Selva
Hello, I was wondering if you could help with the following issue:
The vendor's provided model file has a definition for a parameter (param1) which I would like to override. Both definitions would happen in the same "block" (same level). The way I'm trying to do this, with no success, is as follows:
A. Define a Global Variable in ADEXL as param1 = 0
B. The netlist (input.scs) generated is:
....
parameters param1 = 0
include "vendor's model file" (In this model file a definition of param1 = 1 exists)
.....
C. A warning in "spectre.out" is created:
WARNING (SFE-2297): "vendor's model file": Parameter `param1' is already defined in the same block, previous definition is ignored.
It seems to me that I would need to revert the order of declaration as described in B.,but I don't know how to do it.
Would there another way to do what I'm trying to do?
Thanks,
Wil
Hello,
is there a simple way to extract the netlist from a layout without parasitics without doing the full LVS with Assura?
I am writing the extract.rul file and searching for a way to debug it.
Thanks,
Pietro
Please can any one help me to do this code
"Code to detect PMOS and NMOS device in given schematic and change/overwrite bulk connection of PMOS to vdd! and NMOS to vss!"
Here I'm struck at getting wire information of bulk to source connected mos with respect to PMOS
Hi,
I am using assura for LVS check, the version is : 4.1_USR1_HF12_514
There are errors like:
Error (AVLVSDF-10007) :No property 'modelName' is specified for cell 'pmos'. specify property 'modelname' in CDF for 'auCdl' simulator
Error (AVLVSDF-10007) :No property 'modelName' is specified for cell 'nmos'. specify property 'modelname' in CDF for 'auCdl' simulator
But in CDF editor, I can find the modelname for both pmos and nmos. What is wrong, how can I solve this problem?
Any advice is appreciated! Thank you.
Hello,
After running DC simulatin, when i do Results-> Annotate-> DC operating point it is showing the following warning
*Error* eval:undefined function
Pls help me to fix this
Thanks
I generated an Ocean script from Analog Design Environment | Session | Save Ocean Script. I've been able to run some simulations using this script. But my schematic has a few instances with the same cdf parameter. For example, an inverter has a width and length associated with it. I have multiple instances of this inverter in my schematic and I'd like to programmatically change the values of the CDF variables for each of these inverters from inside my Ocean Script. Is this possible? If not, what is the best way of doing this?
Cheers,
Varun
Hi,
I am working with 16.5. I have three similar blocks - I've defined a property "Room" for components in Schematic - in my design. I have placed and routed one block in it's Room completely. Now, I'm wondering if there is a way that I can replicate those two other blocks just the same as first one? I mean something like a copy and pase. But, I want them to keep their corresponding net name or Ref Des which they have in Schematic. I saw something in 16.6 as module. But, I want to know what should I do in 16.5.
Thanks in advance,
Hossein
Actually i crated a Memristor Model by using VerilogA code. Then i designed logic gates by using the same with different methodology and i got correct simulated output but when i combined all individual logic gates to make a simple 1 bit adder then i got convergence error. I did simulation for 40n sec but i am getting result upto 6-8 ns . Even i am not able to see input pulse. Please help me to short out this problem. Iam attaching my schematic and log file
************************************************
Transient Analysis `tran': time = (0 s -> 40 ns)
************************************************
Trying `homotopy = gmin' for initial conditions.
Trying `homotopy = source' for initial conditions.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 40 ns
step = 40 ps
maxstep = 800 ps
ic = all
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS
Warning from spectre at time = 38.8734 ps during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
Warning from spectre at time = 46.4423 ps during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
tran: time = 1.245 ns (3.11 %), step = 308.4 ps (771 m%)
tran: time = 3.06 ns (7.65 %), step = 93.55 ps (234 m%)
Warning from spectre at time = 3.10126 ns during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
tran: time = 5.205 ns (13 %), step = 205.2 ps (513 m%)
Warning from spectre at time = 6.0115 ns during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
Warning from spectre at time = 6.1008 ns during transient analysis `tran'.
WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.
Further occurrences of this warning will be suppressed.
tran: time = 7.109 ns (17.8 %), step = 204.3 ps (511 m%)
Error found by spectre at time = 8.03662 ns during transient analysis `tran'.
ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. Last acceptable solution computed at 8.03662 ns.
The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol
Top 10 Solution too large Convergence failure:
I(I9.R2:1) = 3.27345 uA, previously 3.28612 uA.
update too large: | -5.69514 uA | > 1.55317 uA + 1 pA
I(I9.I1:p_n_flow) = 3.27345 uA, previously 3.28612 uA.
update too large: | -5.69514 uA | > 1.55317 uA + 1 pA
I(I9.R1:1) = -6.63437 uA, previously -3.59126 uA.
update too large: | 5.63895 uA | > 1.55653 uA + 1 pA
I(I9.I0:p_n_flow) = -6.63437 uA, previously -3.59126 uA.
update too large: | 5.63895 uA | > 1.55653 uA + 1 pA
I(V3:p) = -508.065 uA, previously -508.099 uA.
update too large: | 5.69437 uA | > 2.05796 uA + 1 pA
Top 10 Residue too large Convergence failure:
I(I9.I1:p_n_flow) = 3.27345 uA, previously 3.28612 uA.
residue too large: | 575.245 mV | > 5.45743 mV + 1 uV
The following set of suggestions might help you avoid convergence difficulties.
1. Evaluate and resolve any notice, warning, or error messages.
2. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
3. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
4. Ensure that a complete set of parasitic capacitors is used on nonlinear devices to avoid jumps in the solution waveforms. On MOS models, specify nonzero source and drain areas.
5. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value using the `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.
6. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.
7. Enable diagnostic messages by setting option `diagnose=yes'.
8. Use the `cmin' parameter to install a small capacitor from every node in the circuit to ground. This usually eliminates any jumps in the solution.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.
Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.
Trying `homotopy = gmin'.
Trying `homotopy = source'.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.
Hello,
I am trying to measure total power consumption of my design based on GDI (Gate Diffusion Input) technique.
I want to know that is the procedure for measuring power is same for GDI like, multiplication of Vdd with current supplied by vtg source using calculator.
Please help if this is not the right way of measuring power perticularly for GDI based design
hi,
i'm simuliting a circuit, where i connect 4 switching caps to the port, than i run a psp annalysis to get the input impedance"Z11", and i want to know how spectre do to give such result, it's for helping me understandind how the input impedance behave.
Two different methods give me different curves (Cap. vs DC bias voltage). However, initial value, final value and also the capacitance at zero bias voltage for both methods are the same.
I use ADE L to calculate the capacitance of a varactor in a desired frequency. The first method was to use AC analysis. Taking the imaginary part of the current and dividing by frequency(rad/s) is the capacitance calculated by this method. The other method was to simply using SP analysis and then the imaginary part of Y11 divided by frequency(rad/s) would be the capacitance. I sweep the DC voltage across the capacitor and get the same final and middle values from both methods. However the slope of the curve is about 1.9 times different and I cannot guess why and which one I can trust.
Any idea?
Hi,
I am using IC 6.1.6 and I want to export .s2p file after s parameter simulation. I tried using
sparameter analysis window>options>output parameters >filename.s2p>dtft=touchstone
But no file is saved when I run the simulation.
Hello.
I'm trying to synthesis SPI core, but in the simulation occurs race conditions between signals SPI_CLK and system clock (clk) in "always" block:
always @(posedge clk)
spi_clk_r <= spi_clk;
How to avoid race condition in this case?
thanks