Does anyone know how to remove all the underlines from my ref designators in my schematic. I performed a back annotate and noticed this showed up as some new 'user modified' feature for tracking ref des changes. But I can't seem to find out how to remove the underlines?
Thanks
Our normal process for manual assembly is print out the assembly drawing, the assembler colorizes the assembly drawing so he can easity identify where the parts go, i.e. 100 ohm resistors are red, 50 ohm resistors are blue, the opamp is green, etc.
Does Allegro have a built in function to color code parts based on part number? If not, I think it would be a nice addition to the PCB capabilities as it can save me hours of time.
All,
Thsi poat is re-visited because I couldn't make it work the last time and had to kluge my way through my design. My situation is that I have a FET with a large pin. I need to add an array of 30(6x5) vias in the symbopl on that large pin to use as a thermal array. There was several suggestions but I couldn't get these to work and had to move on. I'm back asking for advise. Any hints will be helpful as I am am coming up on schedule.I'll attach a screen shot that will show the problem.
Thanks,.
Ron Scott CID+
ron.scott@halla.com
Hello all,
I want to call a C function within my systemverilog file using DPI C. I have tried the one step (irun -sv hello.c hello.sv )and it worked very well. But the thing I want to do is to create my own shared object .so, to do this I have tried a 3 steps methodology (ncvlog ,ncelab and ncsim) but it failed when I want to simulate it.
I got this message : ncsim: *F,NOLWSV: Searching for import subroutine "print" in default library libdpi. Unable to load the default library libdpi.OSDLERROR: ./libdpi.so: only ET_DYN and ET_EXEC can be loaded.
Please find in this following paragraph all my files and script to do this.
Thank you by advance,
Jean-Pierre
/////// top.sv
Dear all,
I am facing an issue with Encounter which i do not understand.
In my digital block I forward my clock input to another clock output pin on my digital block.
VHDL : CLK_OUT <= CLK_IN;
The reason why I am doing this is that my digital block creates some outputs (I will name them DIG_OUT here..) which are clocked with the CLK_IN clock port,
These outputs with the forwarded CLK_OUT clock are fed to another separate block somewhere else on chip in the same mixed signal die.
In order to constrain my DIG_OUT ports with respect to the CLK_OUT port i used the following contraints:
First I constrained my CLK_OUT :
create_generated_clock -name clk_output_clock -source [get_ports CLK_IN] -multiply_by 1 [get_ports CLK_OUT]
Then I constrained my output port DIG_OUT:
set output_delay -clock [get_clocks {clk_output_clock}] -max [expr $tSU] [get_ports {DIG_OUT
set output_delay -clock
, where $tSU and $tH represents the worst case setup and hold time of the receiving flipflops in the other digital design further away on the die. Trace length between data and clock lines from DIG_OUT and CLK_OUT to the destination digital block on the die are equal.
After clock tree synthesis, and mapping to the final layout of my final design I can see that encounter has included one clock buffer between the CLK_OUT and CLK_IN port together with some connecting traces. I can see these element in my layout so that is good.
However, Encounter reports show one report which I really do not understand, a no-drivenNets report:
* TODO:
assign_net_CLK_OUT_0
assign_net_CLK_OUT_1
CLK_IN__Exclude_0_NET
The corresponding mapped layout verilog shows a connection from CLK_IN to an clk buffer and the output of the clk buffer to the CLK_OUT pin.
Generated verilog gives this:
cnbfx2 CLK_IN__Exclude_0 (.Z(CLK_OUT),
.A(CLK_IN));
However, it seems as if the connecting traces in the layout are not connected in the corresponding verilog (although they are clearly visible and connected in the layout..).
Can anybody explain me what is happening here and why this only occurs with this buffererd output clock signal?
With kind regards,
Henk
Hi
I would like to know can I create my own toolbar in Layout window?
If yes, what are the basic requirements and how to create??
Thanks in advance..
Sharif
hello everyone,
I have a question about DPI-C , i know i can load a shared object using irun, even if you need to call it libdpi.so to load it . But I want to load several shared object and not only using the default "libdpi.so" ? because i have several shared object corresponding to a function, and i want to call several function from different shared object ...
Is it possible to do this ?
thank you by advance,
Sincerely,
Jean-Pierre
Hello all,
I am new to the using of the pspice model editor, Can anyone help me in giving a brief idea regarding how to model a NEMS switch based on its I-V characteristics.
Please help me in this regard
Thanks
Revanth Rajalbandi
I'm runing Orcad Catpure 16.0 and I'd like to upgrade to 16.6 but the libraries don't seem to be compatible. Does anyone know what the process is to do this?
Also, can I open a 16.6 schematic file and save it in 16.0 format?
Thanks in advance.
Hi All,
I'm PCB designer as if now working on RF card. I have some doubts in RF Design.
1. Why we place Capacitor or inductor in path of Antenna . If required how to calculate the value of Capacitor or inductor.
2. How we need to calcutate the length of trace between antenna to IC .(i.e will Depending on the Frequency or what).
3.Please let me know any basic refrence book or site for RF design Basics.
Any Help will Appreciated .
Thanks in Advance.!!!!!!!!!!!!!!!!!!!!!!!
Good Day,
Pavan Kumar
I can import a netlist from Orcad and it searchs all the library directories for symbols. When I import a other netlist (.tel) the symbols all need to be in that same directory as the .tel file. How can I have it search all the library directories ?
Hi folks, i have a problem where i'm running a transient simulation regression in AMS. I randomise my supply ramp and on very slow ramps my simulation is taking very small step sizes. (time never advances).
In order to try and find the problem, i'm running with the -profile option in AMS and i have "warnminstep" set to 1e-12 in the transient options.
During my simulation at the point where time stops increasing, i get the following:
"Warning: LTE requirements are forcing the step size below warminstep=1e-12 at time ..."
The problem is that this warning isn't particularly good for helping to find the offending connect modules.
Can anyone help?
Thank you in advance.
I'm sorry if this is a basic question, I am new to using encounter.
During synthesis, i set constraints on the clock like clock_latency and uncertainty to synthesize assuming a pessimistic clock distribution. Based on my understanding these parameters make sure to create a pessimistic setting in synthesis to make sure the design meets timing. I understand these so far and mostly how they affect the synthesis and the design.
My main question is, once I move on to place and route in encounter. I feed the
synthesized netlist and a *.sdc file which includes all these constraints to
encounter for place and route. I am able to place and route everything and see
my timing reports. BUT it seems that the timing reports, STILL use these
constraints from synthesis. I feel like they shouldn't anymore, since the clock
tree has already been synthesized in encounter, the tool should just use that
for timing, and not rely on settings I had in synthesis. I was wondering if I need
to set anything special in encounter to make sure that the timing reports
reflect the synthesized clock tree and not the constraints I set in synthesis of
the RTL.
Any feedback anyone can give me would be appreciated.
I see pages for
Are there mulitple products, or just too many names?
What's this called?
Hello,
I have used SpiceIn to import my CDL (which includes MOSFETS, diodes and resistors). I had good results except when it comes to MOSFETs. The issue is related to the fact that my MOSFET devices, in my cadence librasy, have width per finger "wf" and a calculated total width "wt", which would be taken care of by a callback whenever there is a change in "wf" or the multiplier "m".
In my device map I have a mapping from the width "w" in the CDL to the schematic in Cadence as "wf". Since "wt" is not being mapped, the callback assigns to it a default value, which is not necessarily the product of "w" x "m" from the CDL.
So, at this point in order to get the correct value of "wt" I have to query my MOSFET devices and "pretend" I'm making a change just to trigger the callback to do its job. The problem is that my schematic has hundreds of MOSFET instances and I have lots of schematics, so I manual way to do this would be really impractical.
Two questions:
1. Is there a way in SpiceIn to map to "wf" (schematic view) from "w" x "m" (CDL)? if so, how can I do that.
2. Is there a Cadence routine to make the change automatically as described above such that I can cause the callback to recalculate values? with this I could implement a routine to repeat this operation on every device in my schematic.
Any help would be greatly appreciated,
Thanks.
Hello,
I was looking for some help. I am a graduate student who is looking to perform some s parameter analysis on a LNA. The version of cadence licensed to my university (UMKC) is 6.1.5. Most tutorials have the schematic drawn with parts from the library called analogLib. My university seems to only have the NCSU CDK tools and libraries. Is it possible to do s parameter analysis using these libraries? or is there some way to add analogLib to my university's license?
I had this sort of analysis in mind.
https://www.youtube.com/watch?v=uKyoJ3jZbWI
Thanks
Marouf Khan
When I try to export physical, I get a windows error box that says "pxl.exe has stopped working". I click close the program a Design Sync error shows "Error: PXL Failed. Unable to package the design. Do you wish to view the pxl.log file?" If I click yes, it fails to open the documents, presumably because it was never generated. I saw an article that said this could be cause by having multiple paths in the $path environmental variables. I looked and didn't see anything but did a system restore to the last time that it worked anyway. It did not fix it.
Any ideas?
Hi,
I am using assura for LVS, but failed with errors that unbound devices on schematic are IO cells. I met the similar issues that unbound devices are like nmos, pmos, then I solved with "netlisting options --> use model property as device name if model in instparameters".
But here IO cells are unbound cells, I don't know what is the problem with this.
Anybody can help???
Thank you!