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inquiry about the results of the serial capacitors in cadence

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hello. everyone. I am doing the simulation in Cadence(IC6.1.6). Pls see the schematic below. What I want to know is the voltage of each capacitor. In each two circuit,  a 10V vdc , 2u cap and 8u cap. 1Ω resistor are used.  Tran simulation is used by setting 100u. I set initial volatge of all capacitor equal to 0.

After runing the simulation, the c1 always equals to 5V no matter what the value of the two capacitor are in the upper circuit. If I leave the initial voltage of the capacitor blank, the C1 equal to 0V

In the lower circuit, the C2t and C1b equals to 3.5V when 2 resistors are included. 

And by calculation the C1 should be 2V, and the the same with c2t. I don't know why the results are so strange. I have disucessed with many people. but I still could not fix it. Could someone help me? 

 


How do I instantiate a UVM agent with a monitor, functional coverage and scoreboard in a legacy testbench

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Hello all,

 I have a traditional testbench that instantiates a Stimulus Generator and a DUT. Looks like this

//in module tb.v

module tb; 

driver i_driver(...);

dut i_dut(..); 

endmodule

The stimulus generation occurs within the driver.

I would like to add an UVM Environment with only a Monitor, Scoreboard and Functional Coverage to this testbench. I created a wrapper called "svid_packet_monitor" and instantiated that in the tb. 

module tb; 

driver i_driver(...);

dut i_dut(..);

svid_packet_mon_wrapper i_svid_packet_mon_wrapper();

endmodule 

I am new to the whole UVM thing and am not sure how the code inside the monitor wrapper should look like. I took a first stab at creating a package with the monitor and associated class items and  imported this inside the svid_packet_mon_wrapper. Then I created my_test inside the wrapper that extends uvm_test but I am not sure how to start this up. I am attaching the code for the monitor package and  the monitor wrapper( with questions inside the monitor_wrapper code ). Any help to put this together would be highly appreciated...

Best

Raj 

 

Is Cgs= -(Cgg+Cgb+Cgd) or Cgs=-(Cgg+Cgb)?

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Hi,

 I found these two equations in MOS Capacitance Model section from Virtuoso Simlator Components and Device Models Reference.

In trieod region, the first equations works and the second one works for saturation region.

 But in my Print DC table, I copied the values of Cgg, Cgb and Cgd. I find the Cgs always has a value very closer to the result got from trieod region equation verification even I am sure it is working in saturatin region.

Is there anybody who knows why?

 Thanks, 

What is EPSROX (Er: Gate Dielectric constant) in BSIM3v3?

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Hi,

I found Er = 3.9 in BSIM4.5 manual and used in calculation of Cox.
But there is no information of Er in BSIM3v3 which is used in .18um technology.

1. Is Er technology-independent which means it holds of the value 3.9 for all technologies?
2. If there is no such parameter, Er, in old version, how do people calculate Cox (Coxp or Coxe)?

Thanks,

Differential Pair routes with No Gap

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Hi,

I'm using OrCAD PCB Designer and have created differential pairs. When I manually route the pair, the gap between traces is always zero no matter what I set the gap to in the contraints manager. I'm fairly new to this tool so I'm getting a littel frustrated why it does this. I even found another posting that some provided a .brd design with a diff pair and its own CM settings. When I deleted the traces to then reroute them, I found the same problem, the trace gap went to zero! Is this a license limitation or am I missing something? I've created CSet spacing parameters in the CM.

Thanks for any help that someone might be able to provide.

 -KC 

Allegro PCB Editor Report like Condensed BOM report

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Hi,

Allegro Editor ( 16.2)  generates Bill of Material Report(Condensed). The report columns are SYM_NAME,COMP_DEVICE_TYPE,COMP_VALUE,COMP_TOL,COMP_CLASS, QUANTITY and REFDES.

This simplified report gives the quantities and used component REFDES in same line.

For ex.

SYM_NAME   COMP_DEVICE_TYPE                                                                                        COMP_VALUE .... REFDES

0402               CAP_SMD-GRM155R71C103KA88D-0402,10NF_50V,GRM155R71C103KA88D        10NF_50V    .....   C3,C5.....

What I want to do is to genarate a report like this simplified one but with PART_NUMBER not COMP_DEVICE_TYPE. Because COMP_DEVICE_TYPE is always long and does inculde extra information other than PART_NUMBER, I wish to use only the PART_NUMBER intsead of COMP_DEVICE_TYPE.

I have checked every option and could not find a simplified report like this one. QUANTITY doesn't exist in generating reports. I want to see the quantity in one line only. So my report can be like this

SYM_NAME   PART_NUMBER                    COMP_VALUE .... REFDES

0402               GRM155R71C103KA88D        10NF_50V    .....   C3,C5.....

Thank you for your helps.

Ahmet OZSOY

how cadence do to calculate Z11 in a psp analysis

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hi,   

i'm simuliting a circuit, where i connect 4 switching caps to the port, than i run a psp annalysis to get the input impedance"Z11", and i want to know how spectre do to give such result, it's for helping me understandind how the input impedance behave.

PSpice Model for a 4017 Decade Counter?

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 I found the following model code for a CD4017B decade counter, but it doesn't work. I'm getting an error as seen in the attachment. The model code I found is:

*---------
* CD4017B CMOS COUNTER/DIVIDER
*
* CMOS INTEGRATED CIRCUITS DATABOOK, 1983, RCA SOLID STATE DIVISION
* NH 9/8/92      REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES
*
.SUBCKT CD4017B CLK_I CLKINHIBIT_I RESET_I O0_O O1_O O2_O O3_O O4_O O5_O O6_O
+               O7_O O8_O O9_O CARRYOUT_O
+ OPTIONAL: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
*
U17BBUF BUF VDD VSS
+ CLK_I CLK
+ D0_GATE IO_4000B_ST IO_LEVEL={IO_LEVEL}
*
U17BLOG LOGICEXP(13,16) VDD VSS
+ CLK CLKINHIBIT_I RESET_I Q1 Q2 Q3 Q4 Q5 Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
+ CLKINHIBIT RESET CLOCK O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT TOQ3 RST
+ D0_GATE IO_4000B IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+
* BUFFERS
+   CLKINHIBIT = { CLKINHIBIT_I }
+   RESET = { RESET_I }
+
* OUTPUT ASSIGNMENTS
+   CLOCK = { ~(~CLK | CLKINHIBIT) }
+   O0 = { Q5BAR & Q1BAR }
+   O1 = { Q1 & Q2BAR }
+   O2 = { Q2 & Q3BAR }
+   O3 = { Q3 & Q4BAR }
+   O4 = { Q4 & Q5BAR }
+   O5 = { Q5 & Q1 }
+   O6 = { Q1BAR & Q2 }
+   O7 = { Q2BAR & Q3 }
+   O8 = { Q3BAR & Q4 }
+   O9 = { Q4BAR & Q5 }
+   CARRYOUT = { Q5BAR }
+   TOQ3 = { ((Q1 & Q2) | (Q2 & Q3)) }
+   RST = { ~RESET }
*
UFF DFF(5) VDD VSS
+ $D_HI RST CLOCK Q5BAR Q1 TOQ3 Q3 Q4 Q1 Q2 Q3 Q4 Q5
+ Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR
+ D0_EFF IO_4000B
*
U17BDLY PINDLY (11,0,4) VDD VSS
+ O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 CARRYOUT
+ CLOCK RESET CLK CLKINHIBIT
+ O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O CARRYOUT_O
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ BOOLEAN:
+   CH_CLOCK = { CHANGED_LH(CLOCK,0) }
+   CH_RESET = { CHANGED_LH(RESET,0) }
+
+ PINDLY:
+   O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O = {
+     CASE(
+       CH_RESET, DELAY(-1,265NS,530NS),
+       CH_CLOCK, DELAY(-1,325NS,650NS),
+       DELAY(-1,326NS,651NS)                  ;DEFAULT
+       )
+     }
+   CARRYOUT_O = {
+     CASE(
+       CH_RESET, DELAY(-1,265NS,530NS),
+       CH_CLOCK, DELAY(-1,300NS,600NS),
+       DELAY(-1,301NS,601NS)
+       )
+     }
+
+ FREQ:
+   NODE = CLK
+   MAXFREQ = 2.5MEG
+
+ WIDTH:
+   NODE = CLK
+   MIN_HI = 200NS
+   MIN_LO = 200NS
+
+ WIDTH:
+   NODE = RESET
+   MIN_HI = 260NS
+
+ SETUP_HOLD:
+   DATA(1) RESET
+   CLOCK LH = CLK
+   RELEASETIME_HL = 400NS
+
+ SETUP_HOLD:
+   DATA(1) CLKINHIBIT
+   CLOCK LH = CLK
+   SETUPTIME = 230NS
+   WHEN = { RESET!='1 }
*
.ENDS

I think it's missing some lines. Shouldn't there be a line starting with ".model"?

 

Thanks,

Mike 


Probing all terminal currents

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Looking for a skill code to list all terminal currents (including all hierarchy levels). I figure that there exist at least 3 ways to extract this terminal list: (1) schematic hierarchy, (2) netlist, (3) psf file. Either is fine, but advantage of extracting those terminal names from psf is preferable since these are all available terminals for sure. 

Thanks! 

CDF Parameter Passing to the Netlist

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Here is my problem:

 I would like to create the hspiceD (or spectre, doesn't really matter) netlist for a circuit, let us call it depth0. This circuit has a subblock, i0, which is an instance of cell depth1. Inside depth1, there is a resistor and a capacitor. In addition, depth1 has a parameter called myParam (defaults to 1) that I would like to pass to the netlist. In other words, I would like to create a netlist like this:

.subckt depth1 in out
* INPUT:  in
* OUTPUT:  out
* ----------------------------
*.PININFO  in:I
*.PININFO  out:O
* ----------------------------
r0 in out 1e3
c0 out 0 1e-12
.ends depth1

.subckt depth0 in0 out0
* INPUT:  in0
* OUTPUT:  out0
* ----------------------------
*.PININFO  in0:I
*.PININFO  out0:O
* ----------------------------
xi0 in0 out0 depth1 myParam=1

.ends depth0
.end

To achieve this, I have edited the CDF parameters of depth1 (Scope:Cell, Layer:Base). I added a parameter called myParam, type:String, Default Value:1, Parse as CEL:yes, Parse as Number:yes, Store Default:yes. When I build the dept0 schematic and add the depth1 symbol, I can see the myParam parameter in the symbol view. In the Simulation Information of the CDF parameters window, in hspiceD simulator, I added myParam in instParameters section.

When I netlist, I do get the netlist above without the myParam value. In other words, the bold line above in the actual netlist is this:

 xi0 in0 out0 depth1

If in the stop view list, I put schematic, then I do get the bold line as I want, (i.e. xi0 in0 out0 depth1 myParam=1), but then the netlister does not descend into i0, and the netlist file does not include the depth1 subckt at all.

Is there a way to keep both the parameter value and the subckt information in the netlist?

Thanks.

 

Delete large number of shapes efficiently

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I have a large number of shapes that I need to remove from the layout. I find that the delete command seems to take exponenentially increasing amounts of time to run as the number of shapes selected goes up. This creates the perverse situation where it is significantly faster to repeatedly select smaller groups and hit delete than to select them all at once and hit delete. Here's an example:

(note: delete here is the leHiDelete() )

 Select 29,000 objects all at once and hit delete -> ~81 seconds

Manually select a few thousand at a time and delete until all 29,000 are gone  -> 22 seconds

 

That's a huge difference since the 22 seconds includes all the time it takes for me to drag the mouse around in between delete commands. This gets worse the more objects are selected. Is there a more efficient way to do this? I tried writing a recursive delete function that breaks up large lists into smaller ones before deleting, but it doesn't seem to yield any speed improvement:

;; delete alias, speeds up deleting thousands of shapes
procedure( myDelete(@optional objects)
    if(objects == nil
        objects = geGetSelSet()
    );if

    cond(
    (objects == nil leHiDelete())
    (length(objects) < 1000 leHiDelete())
    (t
        info("splitting list of length %d\n" length(objects))
        b = copy(nthcdr(length(objects)/2 objects))
        rplacd(nthcdr(length(objects)/2-1 objects) nil)
        a = copy(objects)
        myDelete(a)
        myDelete(b)
    )
    );cond
)
 

[Help] About the simulation of Wien-bridge OSC.

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The Wien-bridge OSC is as below.

R=1K Ohms, C=1uF, so f=1/(2*pi*R*C)=159Hz. And the BW of the operational amplifier is 9KHz. Theoretically, the OSC outputs a sine wave.

However, the OSC keeps a common voltage, which is another steady state.

Is there something wrong with my simulation setup? Can you help me, please? Thanks a lot.

SoC Encounter - Hierarchical design help

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I am running into an issue while trying to implement a hierarchical design in Encounter. My design has 4 different types of modules instantiated in the top level. After importing the gate level netlist into Encounter, I switch to floorplan mode and see a box for the core and a solid pink box for one of the modules instantiated in my design. The other 3 modules do not show up at all. However, when I open the design browser I see that it lists all 4 modules. I can't figure out why these modules don't show up while in floorplan mode. Can anyone give me some suggestions or guidance? Thanks.

I have a design consisting of 32 bit input pin sitimulis problem

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 I am using spectre as simulation tool , my design have 32 bit input pins how i can assign this bits with values

I use vector file but it works fine with single bit , when i increase radix more than 1 it fails

I use sitimulis file but it also fails 

what is the most effective way to test 32 bit input pins in spectre 

Thanks

inquiry about the results of the serial capacitors in cadence

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hello. everyone. I am doing the simulation in Cadence(IC6.1.6). Pls see the schematic below. What I want to know is the voltage of each capacitor. In each two circuit,  a 10V vdc , 2u cap and 8u cap. 1Ω resistor are used.  Tran simulation is used by setting 100u. I set initial volatge of all capacitor equal to 0.

After runing the simulation, the c1 always equals to 5V no matter what the value of the two capacitor are in the upper circuit. If I leave the initial voltage of the capacitor blank, the C1 equal to 0V

In the lower circuit, the C2t and C1b equals to 3.5V when 2 resistors are included. 

And by calculation the C1 should be 2V, and the the same with c2t. I don't know why the results are so strange. I have disucessed with many people. but I still could not fix it. Could someone help me? 

 


read next line if first charcter is semicolon

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Hi,

I have a file.After importing i want to read this.I want if the first character in a line of the file is semicolon then it should read the next line.

Is there any procedure to do that.

 

Thanks 

 

Windows 8.1 can't install flexID driver

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Hi there, 

 

I hope you can help. I have installed the windows 8 licence manager, this seems to install ok. However at the end of the install a pop up window appears which says the FLEXID 9 Drivers need to be installed. I run the app and install the drivers, restart the computer as prompted but they still haven't installed. 

I can see the HASP HL 3.25 in my device manager, this also states that there is no driver installed. 

 This is for ORCAD 16.6, which ran ok on straight windows 8 before a format and upgrade to windows 8.1. Its driving me mad. 

 

Thanks in advance 

 

Rob, 

attributes

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Hi All,

Using 16.6-S.06 and Design Entry HDL.

I placed several resistors, caps, and inductors. When I look at the parts table for resistors, it looks like this in part:

DESCRIPTION     VALUE     COMP_PROPERTIES          JEDEC_TYPE     TOLERANCE     RATED_POWER     MATERIAL

res0201 0R      0R                Res                    RESC0603X20N                       0.05W       Thickfilm

res0201_10R      10R           Res                    RESC0603X20N         5%               0.05W       Thickfilm

res0201_22R      22R         Res                    RESC0603X20N         5%               0.05W       Thickfilm 

 

But if I select a part on the schematic and look at the attributes it looks like :

VALUE0R

LOCATIONRF_R410

PATHI57

PACK_TYPE<< NULL >>

TOLERANCE?

RATED_POWER?

RELEASE_STATUS?

JEDEC_TYPE?

MATERIAL?

$VARIANT

My question is why do only the Key Properties transfer and not the Injected Properties? I have about 200 CAPS, RES, and IND with this problem. What's the easiest way to fix this so I can generate a netlist?

Thanks!

Bob 

Importing a Shape Symbol using Skill

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Is there a way to import a Shape Symbol 'xxx.ssm' using Skill.  I was hoping to use axlLoadSymbol(), but SHAPE isn't a valid symbol type.

PSS simulation for RF LO and mixer simultaneously

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 Dear Team,

 I am designed RF receiver in cadence. I have simulated oscillator and mixer individual. Now i am trying to simulate simultaneously. But PSS analysis is not running. Because beat frequencies for RF signal, LO signal and IF signal is different. How can i simulate it? Can you please guide me? 

 Regards,

Darshak

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