How do I turn off flighlines from the bulk of transistors....
Hi,I wonder how can I turn off flightlines from the bulk of transistors. Those are very annoying, eventhough I put the guardring around and connect it properly, those flightlines still exists...I use...
View ArticleMonte carlo on a verilog A custom macro model based on device instance not...
Hello, I am developing my own macro model in verilogA module test1 (p1,p2);…endmodule Then I use a model card approach to manage the parameters and their variations: simulator lang=spectresection...
View ArticleVeriloga Montecarlo input from spectre
Dear, I am trying to add montecarlo mismatch into a verilogA model (delay variation) using IC6.1.5.I read on several post to use a custom scs model file that includes the verilog file and has a STAT...
View ArticleFinFET model parameter
I have a FinFET model parameter and I need to use to simulate a circuit. How can I do it? Should I only change the file extension from .pm to .scs and copy it where everything else is? Or should modify...
View ArticlePlotting CMRR and PSRR in cadence virtuoso
Hi, I am designing an Instrumentation amplifier using differential difference amplifier. I want to calculate CMRR and PSRR.Please help me how to plot them using cadence virtuoso.
View ArticleCMRR of an OP amp
Hi, is there any direct analysis like AC, DC analysis to calculate the CMRR of the Op-AMp in virtuoso IC 6.1.5.72..?Thanks...
View ArticleCapacitor Mismatch Coefficient for gpdk 180nm technology
Hi experts,I am designing a 8 bit CDAC for the SAR ADC that I want to design for my masters project. Regarding this, I want to know about mismatch coefficient of capacitors (Ac) for gpdk 180 nm tech....
View ArticleSkill code to automatically map instances via name in layout xl
Sometimes the layout instances don't map with the schematic (vxl clean) even if the lvs comes clean. I have to mannualy go to device correspondance & map them. Is there any skill code that can be...
View Articlegenerating multiple block placements
Is there a skill that could possible generate multiple block placement with just one run?
View ArticleError with Assura QRC using IBM 0.13um SiGe
Hi,I am using cadence verion:ic613and Assura4.1-613 and ext 9.14 I can run Assura DRC and LVS fine but when I run QRC I get the following error. Please help me solve this error. ThanksSriram...
View ArticleVirtuoso XL generate>selected from source issue
I am using IC6.1.5-64b.500.12When I call Instances from schematics to layout using "generate>selected from source", it places the instances multiple times. Also all the instances are placed at...
View ArticlePower net short error during Verilog import
I have some digital design done in Encounter, where all cells have VDD! and GND! pins, however the Global power nets are vdd and vss. The layout was done correctly, all cells have their VDD! connected...
View Articleprinting voltages and currents after transient or dc operating point simulations
Is there a way for me to run a simulation and have it write out a text file stating the voltages and currents of all nodes saved?The simulation would be a dc operating point or a transient where I...
View ArticleGet a .txt file as output in ADE-XL
Hi All, I'm looking to display a .txt file as output in ADE-XL. I'm running an Ocean script on each corner which creates a text file (noise summary) that I can print directly (eg....
View ArticlePreserving structure in RTL Compiler
Dear all,I have a AND-OR structure written in RTL in a module. After the synthesis I see that the same logic is implemented using different logic elements in different modules. In one module I see...
View ArticlePCB Editor
I have been using OrCAD PCB Editor for a short time and haven't really had any major problem. One thing that is very annoying is that when I am moving parts or text on the layout the curser jumps up to...
View ArticleModel Editor - Can't "Extract model"
Hello all!I have opened with Pspice Model Editor Demo a .lib library of an IGBT that I downloaded from a manufacturer and the option "View-> Extract Model" is not enabled. Is it because the model...
View ArticleLVS versus physical Verilog from Encounter, Power Node Mismatch
OK, my battle over the LVS versus the physical Verilog file exported from Encounter continues. Finally, I think I kind of managed at least to get LVS working without quitting with error. i.e. it does...
View Articlemeassuring delay in viva
dear all,I would like to measure delay on signal "gap" simulated on two temp -40 and 125 with "trigger" option like:dly_fr=delay( v("gap") 0.75 1 "falling" v("gap") 0.75 2 "rising" 1 1 t"trigger")I am...
View Articlecadence problem : IP3 and IM3 with PWL
Hello All/Cadence Support, I am having the problem figuring out how to run IM3 and IP3 simulation if the input file is a pwl file. I am easily able to run all other analysis of PSS except...
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