Ravel IDE
Hi there,I come from web devel, with some tcltk, vb, and I've been using NETBEANS IDE for years (come from Eclipse). I'm new to ravel coding, and I've started using Cadence Vier, for ravel...
View ArticleAllegro Constraint Manager
I'm wondering why the Electrical Worksheet is not appering in the Constraint Manager?
View ArticleCan we create a rectangle with the flight layers
Hi, Is it possible to create rectangles of given bbox with the flight layers in layout. Currently i am using marker layer but want to change it to flight layers for neat vissibilty of error. Basically...
View ArticleHow to avoid redefining function
Hai,I have created a application form, which calls so many procedures. there are almost 10 procedures. And I need all these procedures to be executed every time for my form callback. In this case this...
View Articlespectre mmsim simulation issue
Hi Andrew, when simulating a circuit in cadence ic610 i get the below error - Loading /home/daglitch/cadence/installs/MMSIM61/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... cpp: error: unrecognized...
View ArticleHow to ungroup busses in DE HDL Schematic
Hi, I have my project in DE HDL tool and i would like to automatically expand/ungroup the busses.Is there any way to do that?
View ArticleCRT Flyback Transformer (LOPT) Simulation Model???
I am doing my final year project on food preservation by applying high electric field pulses. Now for generating high voltage pulses i have chosen flyback transformer. I need flyback transformer...
View ArticleSuppressing product related warnings
Hi,Is it possible to suppress the warnings that I see when I open any board file which are related to product I choose-the disabled features, as shown in the attached image?Thanks.
View Articlehow to separate a noise contributor in pnoise analysis?
HI folks, My question is:in pnoise simulation, can I activate/deactivate specific voltage sources or instances as only noise contributor? For example, in transient noise analysis, Virtuoso provdes a...
View ArticleInsufficient memory to run PSS analysis - how to resolve?
Hello.I did see that there are three recent threads with very similar titles, but - unfortunately, with completely different problems described. I use up-to-date MMSIM and IC5 (2012_2013 package...
View ArticleSpice
I've made a behavioral simulation in Simulink, now I want to make my design at the circuit level. I was wondering is it possible to model an AMS IC without using library of any specific process in...
View ArticleSnap to grid error
I had a license issue and then after getting the tool back and running every time I invoke a new command the snap to grid goeas away. If I close the program and "move dynamic shapes" then invoke a...
View ArticleHave a question: Footprint with VIA?
Hi, I am doing a high density connector footprint. It has 100 pins. In my layout, I need 4 this type of connector. I add VIA to each pin of footprint.When I place this part, it gives me 100 errors~ of...
View ArticleError Vector Magnitude (EVM) simulation problem in IC615
Hello, cadence community,I've stumbled upon a problem with power amplifier EVM evaluation - EVM is out of adequate bounds. At first I thought that the PA is faulty, but then I decided to create a...
View ArticlePEX error in Assura
Hello, I am using Virtuoso front to back design environment 5.1.41 and Assura version av3.1 (sub version 3.1.7_USR1_HF5) . I created 2 cellviews. First is simple inverter where I generated its...
View ArticleMonte Carlo - Virtuoso IC 6.1.5
Hi,In monte carlo analysis, what is the need for the "monte carlo seeds" field.Is there any result variation for the different number of seeds..Thanks.
View ArticleGRID SPACING
Hi all,regarding changing the grid spacing in the schematic composer & the layout editor of virtuoso.Is the grid spacing dependant on what technology file is attached to the library at the time of...
View ArticleCan I create a input field in a form that behaves like a password field?
Dear Gurus, Tried to Google and search in the forum on this topic but turn up nothing.I'm trying to create a field in a form that allows user to enter a password that will be parsed to an external...
View ArticleHow to make FPGA symbol for schematic
Hi, I saw people make schematic symbol for a complex FPGA(almost 400 pins), and that schematic break one FPGA into many different pages. Like bank1 at the first page, bank 2 at the second page,etc.How...
View Articlenetlist pin order for LVS
Hi,I'm trying to change the order in which a circuit is netlisted for LVS but I got into problems. I've modified the termOrder in the CDF form accoding to the pin order I want and I've place the...
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