Hello,
I am using Virtuoso front to back design environment 5.1.41 and Assura version av3.1 (sub version 3.1.7_USR1_HF5) . I created 2 cellviews. First is simple inverter where I generated its layout , DRC and LVS clean_ PEX was also successfully completed. Second cellview is of power amplifier where its DRC and LVS is clean i..e. schematic and layout is match but I stuck at PEX generation. Here I attached the pcx log file in .doc version(as it only allows to attach files with known formats) and one more thing is my working directory of cellview and layout is 'my file' and for LVS run directory is 'test2' and run name is 'ex2'. If anyone can suggest me on this then I will be very greatful. Thank you.