How to set different accuracy settings for different time periods in...
Hi, I have a circuit which takes some 10us for the initial transients to settle and reach a steady state. Just wondering if can reduce the simulation accuracy to 'moderate' during the initial times...
View ArticleHOW TO CHANGE PIN PROPERTIES?
Hi Andrew,I am changing the pin properties.I want to change lpp of the pin-rectangle which I have generated from schematic.What I am doing npw is , after selecting the pin in layout...
View ArticleAccessing AXL session from a preRun script
Good day. I am trying to determine the section of the model file in a preRun script (i.e. do things like: axlGetModel(), axlGetModelSection()). This requires getting session ID first, so I can call...
View ArticleRegarding PSS and PNOISE analysis: Getting a peak at 1KHz in Noise plot
I am simulating a chopper stabilized opamp circuit in which I need to do noise analysis. As the biasing point is changing with time periodically, I need to do PSS analysis and for Noise PNoise...
View ArticleDo I need termination resistors for low speed RAM?
Hi, I am doing a desing with FPGA and RAM, The RAM is running at about 200 MHZ (Not a DDR3).Do I have to put termination resistors in this design? The PDF file doesn't say anything~~Is there any...
View ArticleAPS changes instance name
Hi, I'm facing kind of an issue here. I'm using Spectre-APS and noticed APS changes the instance name of iterated instances.For example, let's say you have 4 instances in parallel, it's then called...
View Articlemixed Signal simulation using Analog schematic and VHDL behaviour code
Hi, I have a simple question regarding the mixed mode simulation using analog schematic and VHDL code. I don't want to synthesize the VHDL, but only want the behaviour simulation. I have imported the...
View ArticleHow to make FPGA symbol for schematic
Hi, I saw people make schematic symbol for a complex FPGA(almost 400 pins), and that schematic break one FPGA into many different pages. Like bank1 at the first page, bank 2 at the second page,etc.How...
View ArticleWARNING(SPMHNI-184): Device library warning detected.
Hi,I encountered the below error, how to solve this? #1 WARNING(SPMHNI-184): Device library warning detected. WARNING(SPMHNI-198): Problems with device 'PIC16F1829-SOIC20,MICROCHIP TEA'....
View Articlehow to connect signal to a real_vector
Hi, I have some issues with a vhdl code. When I connect signals on an element of a real_vector I have these errors: ncvhdl -work st_lib -ams -message ../sources/systeme_comparateur_ent.vhdl...
View Article[Help] Warnings about metal layers in .map file
Hello All,I need your suggestions the warnings I got in the report after P&R with Encounter. The warning information is as following:Parse map file... **WARN: (ENCOGDS-399): Only 2 layer(s) (M2...
View Articleams vs. spectre - incorrect results
Hello cadence users, I am using C18 CMOS c18a6 technology from AMS - AG hitkit v.ams_4.11. The problem is with different/incorrect results for simulation instance 'sblkndresx' from library esd7rf....
View Articleproblem on simulating the Rflib components
I am using a balun for Diffrential Lna simulation but the simulator produce error due to balun so plz help me how to fix it.Cadence (R) Virtuoso (R) Spectre (R) Circuit SimulatorVersion...
View ArticledbCreateblockage -- returns function cannot found
Hi, I am using dbCreateblockage commnd to make PR blockage in my layout.But virtuoso dont recognize this command. It is there in skill database management document.It says that this is a OA data base...
View ArticleERROR DURING SIMULATION
Sir,First of all, let me thank u for helping me in my project work, by giving valuble information. We are using BSIM-CMG (DG-MOSFET) model for circuit analyses and earlier, we were getting the output...
View ArticleHow to change the pin function in Capture
Hi everbody,I am designning a network schematic and I had problem about the pin function of devices. I want to change the pin function of some IC (example from bidirectional pin to passive pin...). I...
View ArticleLVS issue: short between global net VSS! and gnd
Hi,I' m using PVS 12.1 in IC6 to do LVS and I have that issue: One cell used in the schematic has a global net VSS! and VDD!. In the top schematic and layout,the power is vdd and ground is vss.So the...
View ArticleExample Ocean measurement file in ADEXL
I'm trying to create an ADEXL measurement using an Ocean script and I'm not having a lot of luck. I've been trying to find a simple example but I've yet to see one in the manual or online. Right now...
View ArticleBack Annotation Issue
Hi,While back annotating, I get an ERROR(SPCODD-549) in my swp.log file as follows,#549 ERROR(SPCODD-549): No physical part found for COMP_DEVICE_TYPE=AD5232_TSSOP16_TSSOP16_IC_1.2MM, regenerate the...
View Articleerror in "if" statement
Hi, the error is: E- *Error* if: too few arguments (at least 2 expected, 1 given) - (member(via_net net_list)) code: net_list=list("VDD" "VSS") sel_via_dbid=axlGetSelSet();listing the selected via's...
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