mixed Signal simulation using Analog schematic and VHDL behaviour code

Hi,

 I have a simple question regarding the mixed mode simulation using analog schematic and VHDL code.  I don't want to synthesize the VHDL, but only want the behaviour simulation. 

I have imported the VHDL code in the CIW, it generates cellviews:  entity, symbol etc.  But no functional views.  I used before verilog + schematic simulation in the ADEL,  in the config file, the functional file should be used for the verilog code, such that the mixed mode simulation can be carried out.  None of these generated views from the VHDL code can be used in the config file.

 Does anyone can tell me what should I  do to implement such simulations.  I am using cds615 and ius82.  The simulator is AMS is the ADEL.

Thans a lot in advance.