I am using Orcad Layout 9.0 and am getting alot of off-grid via errors. I have changed the grid several times with no sucess. I am trying to route to a footprint that has 1mm pitch. Please advise.
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off-grid vias
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Changing spacing constraints when opening Allegro
Hi All,
I was wondering if anyone can guide me in the right direction.
I'm trying to make it so I can set the bottom SMD pin to TH distance when allegro starts up. This will need to be done to all files being opened.
I'm not familiar with writing skills, but I was wondering if anyone has ran into similar Skill file or at least guide me in the right direction.
I looked through some forum and it looks like I can use axlCmdRegister and axlTriggerSet commands to run the skill automatically once I have the skill file create.
I think this command is where I need to get started from, but I don't think it's that simple.
axlCNSSetSpacing("" TOP 'Thru Pin_SMD Pin .050 INCH)
Any help will be appreciated.
Thanks!
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Synthesis in rclabs using slow and fast library
Hi good morning all,
i have written a code for inverter chain and synthesized using slow and fast lib sepaerately,which represents slow path and fast path helpful in timing analysis.
problem is how can i use this fast lib and slow lib together so that me inverter chain should select perticilar cells from slow lib for slow path and perticular cells from fast lib for fastpath simulataneously..............
please reply.........i need it urgently........
mahesh
9739436239
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RTL Compiler, Min Libraries and CPF
Hi,
For synthesis (RTL compiler) I define a worst case libraries read_cpf -libraries, and in the CPF I use
define_library_set -name my_lib_set _librares {libA_slow.lib libB_slow.lib libC_worst.lib}
i.e. I load multiple worst case librarie (there are actually about 15, from different vendors)
I then export the CPF for the backedn. This works, but....
My backend engineer is complaining that the CPF file does not contain the min libraries.In principle, I just add then in the same way, but I need RTL compiler to ignore the min libraries.
How do people usually manage this issue ?
Thanks for suggestions/links
Steven
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PHASE_TOLERENCE?
Hi all,
why we have adjust the phase tolerence between D+ and D-?
what is the difference between static and dynamic phase tolerence?
Anyone please guide me.,
Regards,
Karthik.
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Addition of Noise file to input voltage source of Cadence Spetcre
Hi.,
I am facing problem in adding noise in transient analysis in cadence spectre .
Can help me how to add noise as input source for transient analysis using simulator cadence spectre .
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create the multiple instance in parallel
Hi all,
i draw a sub-circuit, and i would like it to be a sybmol, so that i can implement it in the top level circuit, so my question is how can i create a multiple "self design symbol" in parallel but i don't want to draw them one by one, i notice that people can specify the "m=10" (multiple) parameters to achieve this when they want to use the ten capacitor connect in parallel, but i fould there is no "m" parameter when i use my own symbol, so what i can do for this? some guys said that we can specify the instance name[1:10] for this, but it doesn't work in cadence when i try to perform the simulation from ADE using the spectre simulator. welcome to your suggestion.
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How to know if a terminal pin is in the left,right,top and bottom of a circuit symbol?
Hi All,
How can I know if a terminal pin is in the left,right,top and bottom of a circuit symbol? and how to count them?
ex.
left - 13 terminal pin
right - 10 terminal pin
top - 2 terminal pin
bottom - 0 terminal pin
Thank you very much in advance.
Best Regards,
Reinice
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Schematic p-cell for modelling parasitic resistance and capacitance
Hi,
I'm looking for a schematic p-cell which models parasitic resistance and capacitance in layout.
A former employer of mine had this function; to model a metal wire or interconnect in the layout, you'd place a special p-cell in your schematic, enter in which metal layer it was placed, add length and width as well as surrounding density, and the p-cell would pop out with a calculated RC value and act as a lumped resistor and capacitor. This was incredibly efficient in pre-layout simulation of routing-sensitive modules.
Is there built-in support in Cadence for such a function, or will I have to write a p-cell from scratch myself?
Best regards,
Tore
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a question about cell characterization
how does ELC examine the syntax of input netlist?
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How to view adexl in GUI mode?
Hi All,
I' am running ocean XL in batch mode. I use ocnxlSaveSetupAs function to create the adexl view. Here's the context using the function:
ocnxlSaveSetupAs("myLib" "myCell" "adexl")
My runs are finishing/executing fine during batch mode. When I try to open the generated adexl in GUI mode, It's always the "Welcome to ADE XL" that I' am seeing. I can't view the generated adexl and there are no Tests in Data View tab. How can I view my generated adexl(using batch mode) in GUI mode?
Thanks and Regards,
Reinice
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axlSingleSelectPoint not accurately !
Hi all!
I'm writting a skill to check at start point & end point of a cline if pin exist or not, if pin exist and pin's netname ="dummy",
then assign that cline to that pin. AND , if the coordinate is in the restrict area (box_xy) then do nothing. But I got the problem,
when I put the code to get restrict area, the code still run but the function axlSingleSelectPoint not accurately, otherwise, it's ok.
Who can show me where's wrong? and how can I fix it?.
..............
; =====Get box xy, (default: leftdonwn- rightup)=====
box_xy = axlEnterBox(?prompts list("First rectangle point, please...", "Second rectangle point, please..."))
axlClearSelSet()
loc1_x = xCoord(car(box_xy))
loc1_y = yCoord(car(box_xy))
loc2_x = xCoord(cadr(box_xy))
loc2_y = yCoord(cadr(box_xy))
;=====process if user pick from any coner for making axlEnterBox()=====
if(loc1_x < loc2_x && loc1_y < loc2_y then
box1x = loc1_x
box1y = loc1_y
box2x = loc2_x
box2y = loc2_y
else
if(loc1_x < loc2_x && loc1_y > loc2_y then
box1x = loc1_x
box1y = loc2_y
box2x = loc2_x
box2y = loc1_y
else
if(loc1_x > loc2_x && loc1_y < loc2_y then
box1x = loc2_x
box1y = loc1_y
box2x = loc1_x
box2y = loc2_y
else
box1x = loc2_x
box1y = loc2_y
box2x = loc1_x
box2y = loc1_y
);enf if 1
);end if 2
);end if 3
;=====Prepare =====
axlSetFindFilter(?enabled '(noall pins) ?onButtons '(noall pins))
axlClearSelSet()
axlVisibleDesign(nil)
axlVisibleUpdate(t)
axlVisibleLayer("Pin/top" t)
axlUIWUpdate(nil)
axlClearSelSet()
;=====Main process=====
foreach(clines allWiresInDesign
netname = clines->net->name
if(stringp(netname) then
when(nindex(netname, "__")
;=====get location xy at start cline & end cline=====
cline_seg = clines->segments ;get all segment in a cline
first_seg = car(cline_seg) ;get first segment
last_seg = car(last(cline_seg)) ;get last segment
first_seg_xy = car(first_seg->startEnd)
last_seg_xy = cadr(last_seg->startEnd)
x1= xCoord(car(first_seg->startEnd))
y1= yCoord(car(first_seg->startEnd))
x2= xCoord(lastelem(last_seg->startEnd))
y2= yCoord(lastelem(last_seg->startEnd))
;===CHECK LOCATION X1:Y1 IF PIN EXIST OR NOT=====
if(and(x1>box1x, x1<box2x, y1>box1y, y1<box2y) == nil then
pinselect = axlGetSelSet(axlSingleSelectPoint(x1:y1))
axlClearSelSet()
if( pinselect != nil then
pinselect = car(pinselect)
sym_name = pinselect->component->name
pin_net_name = pinselect->net->name
pin_number = pinselect->number
if(pin_net_name == "" then
fprintf(writeOutFile, "%s %s\n", "FORM mini netlist ", netname)
fprintf(writeOutFile, "%s %s.%s\n", "FORM mini pinname ", sym_name, pin_number)
fprintf(writeOutFile, "next\n")
);endif
);end if pinselect==nil
);end if
;===CHECK LOCATION X2:Y2 IF PIN EXIST OR NOT=====
if(and(x2>box1x, x2<box2x, y2>box1y, y2<box2y) == nil then
pinselect = axlGetSelSet(axlSingleSelectPoint(x2:y2))
axlClearSelSet()
if( pinselect != nil then
pinselect = car(pinselect)
sym_name = pinselect->component->name
pin_net_name = pinselect->net->name
pin_number = pinselect->number
if(pin_net_name == "" then
fprintf(writeOutFile, "%s %s\n", "FORM mini netlist ", netname)
fprintf(writeOutFile, "%s %s.%s\n", "FORM mini pinname ", sym_name, pin_number)
fprintf(writeOutFile, "next\n")
);end if - (1-24)
);end if pinselect==nil)
);end if
);end when
);end if stringp
);end foreach via allWiresInDesign
.........
Tks!
Luan.
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Run Skill Scripts and Update Schematics from Unix Command Line
Can we load and run skill procedures without having to invoke interactive command window. I have started to read about "interprocess communication" but it looks like these need to be run from the CIW window.
Thanks
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[PCB Designer] Shape toolbar
Hi all,
When I select the shape toolbar under PCB Designer, I only have the "delete island" button on it. How could I show the other buttons ?
Many thanks for your help and kind regards,
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latest Specman-Matlab package
Attached is the latest revision of the venerable Specman-Matlab package (Lead Application Engineer Jangook Lee is the latest to have refreshed it for a customer in Asia to support 64 bit mode. Look for a guest blog post from him on this package shortly.)
There is a README file inside the package that gives a detailed overview, shows how to run a demo and/or validate it’s installed correctly, and explains the general test flow. The test file included in the package called "test_get_cmp_mdim.e" shows all the capabilities of the package, including:
* Using Specman to initialize and tear down the Matlab engine in batch mode
* Issuing Matlab commands from e-code, using the Specman command prompt to load .m files, initializing variables, and other operational tasks.
* Transfering data to and from the Matlab engine to Specman / an e language test bench
* Comparing data of previously retrieved Matlab arrays
* Accessing Matlab arrays from e-code without converting them to e list data structure
* Convert Matlab arrays into e-lists
Happy coding!
Team Specman
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import cdl file in schematic
I would like to import cdl file but i have problem. What is the map file? How I can to import cdl file?
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Generating Reports
Hi,
Where can i see what are the most important reports to generate after each step? (floorplan/placement/cts/routing/post rout)
Thanks!
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Teaming up on a Design
I'm looking for some guidance on the following. A co-worker and I have teamed up on a fairly intense 12 layer design (controlled impedance, DDR, tuned traces, 684 ball BGA, etc) My partner is responsible for placement, routing and meeting all of the technical design challenges and I am responsible for cleaning up the design cosmetically (silk placement, fab dwgs, assy dwgs etc) and preparing it for release to fab and assy. I am aware that there are features within the tool (v 16.5) that enable a team approach to the design (sub-drawings, clip files, etc) but I have very little experience using those features toward this end. Can anyone clue me in to documentation or tutorials that may be available for accomplishing this? A sincere thanks in advance for any help you can provide.
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Reg .VCD file generation
Hi,
I need to run power analysis . so i need .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need some steps....i asked in digital forum they requested me to post here... i.e in this forum...
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Help and apologies...
First, apologies if this is in the wrong area...
Question.
I am attemtping to follow the online tutorials for the creation of component symbols and importing a csv file of a component i wish to create. There are 3 columns, Name, Type and Pin.
The issue is that every time i attempt to import the data, i get the message saying i have to change to the Xl license option. However i am reliably advised that this is not necessary as it only provides additional features and should not prevent me being able to import the files. However i cannot proceed beyond this point.
Please could someone confirm either way and point me to the correct area if i am in the wrong location
Kind Regards
John
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