Failed to build VDB

July 23, 2012, 2:42 am

≫ Next: Problems with custom pad shape...

Hi all,

I have installed a PDK and set some settings in Switches in DRC form. I have been getting below warnings in CIW while running DRC.

Warnings:

Assura DRC: State saved "Last"
Compiling rules...

ERROR Wrong techLayers() item in techfile: (MT3_noconn 1084)
Layer# must be an unsigned integer between 0 and 255.
WARNING Undefined layer in dfII.
   Layer name 'prBoundary' doesn't exist, treating as an empty layer.
   PRBound = layer("prBoundary" type("drawing"))

WARNING Undefined layer in dfII.
   Layer name 'M3_noconn' doesn't exist, treating as an empty layer.
   M3_nodummyi = layer("M3_noconn" type("no_dummy"))

WARNING Undefined layer in dfII.
   Layer name 'M4_noconn' doesn't exist, treating as an empty layer.
   M4_nodummyi = layer("M4_noconn" type("no_dummy"))

WARNING Undefined layer in dfII.
    Layer name 'MT' doesn't exist, treating as an empty layer.
    MT_ll = textToPin("MT" type("label"))

WARNING Undefined layer in dfII.
    Layer name 'MT' doesn't exist, treating as an empty layer.
    DMTi = layer("MT" type("dummy"))

WARNING Undefined layer in dfII.
    Layer name 'MT3_noconn' doesn't exist, treating as an empty layer.
    MT3_msi = layer("MT3_noconn" type("mslits"))

WARNING Undefined layer in dfII.
    Layer name 'MT3_noconn' doesn't exist, treating as an empty layer.
    MT3_lsi = layer("MT3_noconn" type("lvs"))

WARNING Undefined layer in dfII.
    Layer name 'MT3_noconn' doesn't exist, treating as an empty layer.
    MT3_nyi = layer("MT3_noconn" type("no_dummy"))

WARNING Undefined layer in dfII.
    Layer name 'MT3_noconn' doesn't exist, treating as an empty layer.
    MT3_opci = layer("MT3_noconn" type("opc"))

info: dubiousData is handled by default in Assura.
1073. dubiousData("M1")
*WARNING* (reader): extra ')' ignored at line 2751 of file /remote/projects/semtech/ts18pm/CDB/HOTCODE/techs/ts18pm_3M1T3/assura/default_scr/../../../ts18pm/assura/default_scr/DRC_TS18SLPM_ASSURA
*WARNING* (reader): extra ')' ignored at line 3825 of file /remote/projects/semtech/ts18pm/CDB/HOTCODE/techs/ts18pm_3M1T3/assura/default_scr/../../../ts18pm/assura/default_scr/DRC_TS18SLPM_ASSURA
WARNING Duplicate errorLayer 'DEV_fuse'; latter replaces former.
8028. errorLayer(DEV_fuse "MEF.N.1: metal eFuse is allowed in metalization options per design rule")
Errors exist in the rules file '/remote/projects/semtech/ts18pm/CDB/HOTCODE/techs/ts18pm/assura/t.00_00_01_scr/DRC_TS18SL_ASSURA'.
*WARNING* Failed to build VDB. Cannot submit DRC Run.

Assura DRC: State loaded "Last"

Thank you,

sarvani

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Problems with custom pad shape...

July 16, 2012, 8:36 am

≫ Next: An unidentified pcb component

≪ Previous: Failed to build VDB

Hi Group!

I'm using Orcad PCB (Tiny-Allegro ;-) version 16.2 s28.

I've drawn some custom shapes for pads/soldermask (Halfcircle2mm.ssm and Halfcircel2mm-sm).
When I load them in Padstack Designer (as "Shape" with "Geometry" dropbox="Shape") the preview of the pad is just a vertical line, the soldermask looks like the drawn (but hollow). This seems a bit strange - but preview functions has never been a Cadence selling point. The the "Top" view of "Views" in Padstack designer is just a square - but I think thats a feature that has never worked with custom shapes anyways (?).

Using the padstack (Halfcircel2mm.pad) in a footprint looks as expected. But when placed on a board it seems the soldermask is used for the actual pad. In any case the outline is to big (and pin center is not where it should be).Thus the pads are shorted (and I get the expected "SMD Pin to SMD Pin Spacing" DRC).

I'm at the point where I think I've tried everything at least twice - but I'm hopefully just missing something obvious?

Any input greatly appreciated!

Best regards,
Anders Frederiksen (Denmark)

PS: Relevant design files and a screen shot of the footprint in the editor and placed can be found here http://hi5.dk/Temp/CustomPad-failing.zip

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An unidentified pcb component

July 27, 2012, 3:43 pm

≫ Next: Struggling to create PCB layout, missing footprints.

≪ Previous: Problems with custom pad shape...

Hi,
Could someone help me in identifying the component in the attached picture. I guess it is a regulator. I am trying to understand whether it is faulty or not. The input is around 5V and the output is 0. Thanks..

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Struggling to create PCB layout, missing footprints.

July 21, 2012, 12:17 pm

≫ Next: Where do I ask PSpice questions?

≪ Previous: An unidentified pcb component

Learning orcad. Created a project in capture using pc board wizard.

Drew simple circuit containing a BZX84C12/ZTX zener from the zetex library that shipped with orcad.

Following instructions from http://encon.fke.utm.my/nikd/PSM1/PCB_layout/PCBorcadpcb.pdf exported layout netlist.

Trying to create project in Layout (or Layout Plus or Layout Engineer's Edition or Layout PSpice Orcad Ultra A/D Super Duper or Layout Engineer University Edition Plus Japan or whatever tool I'm actually using).

It says no footprint for component. I try to link existing component. I pick one with two pads e.g. DAX/1N_4001-4007 from TM_DIODE.

Error says "electrical package bzx84c12/ztx forcomp d1 has at least one pin (1) which has no corresponding pin on footprint". Unclear as to how to proceed, as component has two pins, footprint has two pads, component is a diode, and footprint is from a library for diodes.

Please advise as project is now on hold.

Thanks.

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Where do I ask PSpice questions?

July 19, 2012, 5:12 pm

≫ Next: "ERROR -- Invalid Device" and invalid netlist from capture.

≪ Previous: Struggling to create PCB layout, missing footprints.

What forum do I ask PSpice A/D usage questions in? I didn't see a forum for software questions in the list.

Thanks.

↧

"ERROR -- Invalid Device" and invalid netlist from capture.

July 28, 2012, 9:41 pm

≫ Next: Creating SUBCKT model with model editor.

≪ Previous: Where do I ask PSpice questions?

I created a subckt part in a pspice library. I am attempting to use it in capture/pspice. Running a simulation produces "Error -- invalid device" in pspice. The netlist that capture generates looks like this:

* source PS2
R_R2         N00316 0  1k  
R_R3         N00332 0  1k  
R_R4         N00368 0  1k  
V_V1         N00117 0 10
1665,        
R_R1         N00193 0  1k

Where the "1665," is the offending line. Now what?

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Creating SUBCKT model with model editor.

July 28, 2012, 9:43 pm

≫ Next: HTML editor in new post broken, like everything else.

≪ Previous: "ERROR -- Invalid Device" and invalid netlist from capture.

I have only managed to create a new subckt model by importing an existing subckt from another library then editing it.

Where is the "new subckt model" command in PSpice?

Thanks.

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HTML editor in new post broken, like everything else.

July 28, 2012, 9:47 pm

≫ Next: can the same network have two names?

≪ Previous: Creating SUBCKT model with model editor.

Google Chrome latest version, Windows 7 64-bit

Create a new forum post. Press HTML button and edit with valid HTML. Press Update. Message window becomes solid empty gray block. Pressing "Post" will still post the message, but there is no way to edit or even view it after pressing Update on the HTML editor.

Note that pressing back button on browser after making the post will return to the new post page with the message window enabled and containing the message, properly formatted and editable.

Cadence you have enough trouble trying to design stable and functional PCB layout software. Please consider using one of the many mature and well-established forum systems that already exist instead of attempting to create your own, which, based on the QA I've seen, is basically doomed to fail from the start.

↧

can the same network have two names?

July 28, 2012, 9:59 pm

≫ Next: How to enable psfxl output with AMS sim in ADE L?

≪ Previous: HTML editor in new post broken, like everything else.

Using Orcad Capture 16.2
My design is hierarchial.
On one block sheet (call it sheet 1) I have a power net - assume it is called NET1
NET1 is used on another block sheet (call it sheet 2), however on that sheet it is also connected to a hierarchal port - assume the port is called NET2
This is done for better understanding of the circuit operation.
When generating the netlist two nets are generated - all components on sheet1 appear on NET1 and all those in sheet2 appear on NET2.
Is there a way to force the system to understand that these two nets are actually one net and generate a single net in the netlist?

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How to enable psfxl output with AMS sim in ADE L?

July 28, 2012, 5:30 am

≫ Next: Constraints Manager DIFF pair length match between p/n

≪ Previous: can the same network have two names?

I'm using AMS simulation thru ADE L in IC615.500.10 and want to enable psfxl format as transient output which is claimed to be supported. But I don't found any check box or selection in Outputs - Save All form.

Anyone knows how to enable psfxl? Thanks!

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Constraints Manager DIFF pair length match between p/n

July 30, 2012, 6:11 am

≫ Next: Stream in warning

≪ Previous: How to enable psfxl output with AMS sim in ADE L?

Dear all,

I am using Allegro 16.5.I need to match the etch length between P & N of diff pair in the pcb editor.

Regarding this i want to set the value in constrsint manager.The match tolerance/difference is 1 mil.

Example: diffpair_1 is running around 1000 mils.Here i want to match the etch length of P (+) & N (-).

Which one is travel very long either P or N ,based on that i want to match the smaller one with the 1 mill tolerance value.

If the etch length ,P = 1000 mils means , N = 999 to 1001 mils

Regarding this 1 mil tolerance value ,how can i set in the constraint manager for all diff pairs by using formula or any other method.

Thanks in advance....!!!!

↧

Stream in warning

August 3, 2012, 1:13 am

≫ Next: Allegro PCB Legacy 16.5

≪ Previous: Constraints Manager DIFF pair length match between p/n

Hi,

I have a SRAM memory instance which is generated using a compiler. while streaming it in I am getting the following warning

"WARNING (XSTRM-80037): A zero-area polygon was encountered and ignored." for a particular leaf cell in the design.Can anyone tell me why is this happening and a solution to fix this problem.

Regards

Vipin

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Allegro PCB Legacy 16.5

August 2, 2012, 2:55 pm

≫ Next: Signal integrity verification at 10GHz

≪ Previous: Stream in warning

When I open a brd file from Expert with Legacy how can I keep the drcs from being so massive when all I need to do is review the board.

I do not want to go thru the trouble each time try to clear thousands of drcs that do not exist in the Expert version.

Even though I have had the Cst.Mgr. extracted and imported into the Legacy version it seems the the constriants still get changed. Is there a fix for this?

↧

Signal integrity verification at 10GHz

July 18, 2012, 2:33 am

≫ Next: How to find the final time value of a signal?

≪ Previous: Allegro PCB Legacy 16.5

Hello,

Is Allegro PCB SI (or some other tool from 16.5) capable to check signal integrity of a complex board at 10GHz ?

Or one should export the board file to HyperLynx and check SI with the last one ?

Thanks in advance.

Pavel.

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How to find the final time value of a signal?

August 3, 2012, 10:31 am

≫ Next: IRUN and PlusArgs

≪ Previous: Signal integrity verification at 10GHz

( I did search the forum and support.cadence.. no luck)

Say my simulation terminates earlier than the input file specifies, I want to analyze the last 10 us of a waveform.

How can I get tmax, which is the final timepoint?

xmax gives the time value corresponding to the max value that the signal attained.

Thanks

↧

IRUN and PlusArgs

August 3, 2012, 10:57 am

≫ Next: segment error for symbol

≪ Previous: How to find the final time value of a signal?

I am having issues trying to pass a $plus$args using IRUN. Anyone have any clues? Can we NOT use the +plusarg on irun command line?

------------------------------

irun command line:

** irun -file simopts/rtl_opts.def -file chipfiles/chip_rtl.h -file chipfiles/chip_tb.h -top test -input scripts/core_test.rtl.0.tcl +mytest

Code snippet to check for +mytest

------------------------------

// Code snippet to check for +mytest

if ($test$plusargs(“mytest”)) begin

$display("FOUND MYTEST");

end

// Here is what I see on the failed attempt to run simulation, which appears during elaboration step.

         Top level design units:
                test
if ($test$plusargs(âmytestâ)) begin
                              |
ncelab: *E,CUVHNF (./tbsource/tb_test_apcm_demo.sv,39|30): Hierarchical name component lookup failed at 'mytest'.
irun: *E,ELBERR: Error during elaboration (status 1), exiting.

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segment error for symbol

August 3, 2012, 11:43 am

≫ Next: Virtuoso Analog Distributed Processing Option with SGE

≪ Previous: IRUN and PlusArgs

Hello,

I wrote a veriloga code for some behavioural modeling. It compiled fine and let me create a symbol. I then instantiated the symbol and tried to sim it with spectre. The spectre simulation bombs and the error message is like "segment error for symbol: pin_name" and it is referring to a line that is located after the veriloga code ends(endmodule). Does anyone know how to get around this problem ?

Regards,

Uzzy

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