Hi everyone,
do you need to display your memory in a table or a form, or is it other way to display my data store in memory, i want to show the data to my customer, can you give me some advice, welcome to discussing about this.
Regards,
zfeng
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can we create a table or form to display my data in memory, looks like "excel" shows?
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User Interface - How to create a table with ComboFields in a Form?
I would like to create a table such as the one in the attached image.
The table should have read-only text boxes, such as a ReportField, but it also should feature ComboField entries to allow the user to select between two or more options.
Please see the attached image to understand the appearance of this table.
I have searched the extensive documentation about creating User Interfaces in SKILL but I did not yet manage how to create such a table...
I would really appreciate some help on this.
Thank you
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VerilogA compiler
Dear all,
I'm using VerilogA model in my design in Cadence, I have some variables in the model that should be changed with time, actually I have two questions:
1- Is there a way to display the value of those variables during the analog simulation? I was looking for VerilogA compiler to test my code first but I didn't find, can some one suggest me a website or any information?
2- The statement of @(initial_step), does it mean the command after it will be exceuted only one time, which is the begining of the simulation?
Thank you in advance,
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PCB Editor and "find"
When using the "find" feature, is there a way to have the screen go to the part you are looking for? Example, I'm zoomed in on a specific part of the board. I want to locate a part so I use the "find" feature and type in the reference desiginator. The screen remains where it is and I don't know if the part was found or not. Once I zoom out and start looking around, I see that the part that I was looking for was highlighted, but I was never taken to it. What use is the "find" feature if it does not take you to the part?
Example, in 15.7 hit "CTL-F" then type in the reference desiginator and return. You will be taken to that parts location.
Tom
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Creating new attributes and sub-attributes
Hi Everyone,
I would like to add an attribute, for example to a cellview Cv.
The attribute should have itself other attributes, and so on.
It should work therefore similarly to the well-known
Cv~>shapes
which can be called again like this:
Cv~>shapes~>points
or like this:
Cv~>shapes~>lpp
Summarizing, given a cellview Cv I would like to create MyNewAttribute, MyNewSubAttribute1 and MyNewSubAttribute2 such that I can call them by writing:
Cv~> MyNewAttribute~> MyNewSubAttribute1
Cv~> MyNewAttribute~> MyNewSubAttribute2
I know the command dbCreateHierProp(Cv "MyNewAttribute") but I have two problems using it:
1. It stores MyNewAttribute not directly under Cv, but under Cv~>prop. This is just an esthetic problem since the command Cv~>MyNewAttribute still works, but the command Cv~>? does not show MyNewAttribute (which is very unpractical)
2. I cannot create MyNewSubAttribute1
How can I do?
Thanks a lot in advance for any suggestions,
lkphoto
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Bindkey to change via (ex:M1_M2 to M2_M3)
Hi all,
Can anyone please help me on this, how to change the vias using bindkey. For example i am having M1_M2 via in my design. And i want to change the via M1_M2 to M2_M3 via using bindkey. Please help me how to do this.
Thanks,
Karthik.
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After footrpint creation the deleting the existing boundary lines problem occurs?
Hi..
I had created the footprint,which is been recommended on the data sheet. Then i had try to put the shape of silk screen top outline. But that time the shapes are not getting vanished.I had select the option of shape------> select shape or void, then i select the shape, tried to delete vertex by edit---->delete vertex ,but the shape vertex is been not get vanished.
Then how to increase the shape width of the outline in the SST, SSB, AST, ASB layers.In case if i am using the SST layer for the option i had used the solid fill.For the board geometry the at outline----> Line Front option------> what option have to been give. I had tried on solid fill and hidden option. In general case for outline option what have to been provided.any solutions please.
Thanks & Regards
Dhamodharan.
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Assura LVS errors
Dear All,
We are switchig to ASSURA (sub-version 4.1_USR4_HF3) from CALIBR.
But we are seeing following errors in LVS log file. These errors were NOT shown by CALIBRE.
1:-
Executing: nnbdif = geomButtOnly(nsd ptap diffNet)
errorLayer(nnbdif " nsd/ptap butting issue: nsd/ptap need to be connected by metal and contact")
2:-
Executing: ppbdif = geomButtOnly(psd ntap diffNet)
errorLayer(ppbdif " psd/ntap butting issue: psd/ntap need to be connected by metal and contact")
3:-
Executing: ptap99 = geomAvoiding(geomGetNet(ptap PWR1 PWR2) geomOr(CSYMBOL DSYMBOL BJTSY...
errorLayer(ptap99 "ptap is wrongly connected to POWER ! ")
4:-
Executing: ntap99 = geomAvoiding(geomGetNet(ntap GND1 GND2) geomOr(CSYMBOL DSYMBOL BJTSY...
errorLayer(ntap99 "ntap is wrongly connected to GROUND ! ")
Can anybody please tell what are the causes of these errors.
Kind Regatrds,
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Allegro Symbol creation Error
Hi,
I am using 16.6 to create my symbol. When I try to save it I receive below message and PCB editor doesn't save my new symbol anylonger:
(---------------------------------------------------------------------)
( )
( CREATE SYMBOL )
( )
( Drawing : SO-4.dra )
( Software Version : 16.6P004 )
( Date/Time : Sun Jul 06 17:10:06 2014 )
( )
(---------------------------------------------------------------------)
Create Symbol of type: PACKAGE
Directory = F:/OrcadProjects/Symbols
Name = so-4.psm
User = m
Machine = MR
Create symbol started.
WARNING(SPMHA1-269): Shape has no segments. 66078400
SHAPE @66078400
1) mask = 40
2) class = 6 = ETCH
3) subclass = 0 = TOP
4) branch_link = 66078344
5) branch_ptr = 66078344
6) symbol_ins_link = 0
7) first_connection = 0
8) first_void = 0
9) first_outline_seg = 0
10) first_patch_set = 0
11) shape_fill = 1
12) first_text = 0
13) first_relation = 0
14) extents.min = (0 0)
15) extents.max = (0 0)
16) prev_branch_item = 66078344WARNING(SPMHA1-269): Shape has no segments. ERROR(SPMHA1-291): Create symbol has been aborted.Does anybody know the reason?
Thanks in advance,
Hossein
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Drawing path using SKILL
Hello,
I have modified a SKILL file to draw a path from one point to another. However, this function takes two arguments: starting and ending point.
I was wondering if it is possible to write the corner points to make it really look like a path.
Here is the code:
http://pastebin.ubuntu.com/7722058/
Currently, when we specify another location after the end point, we see a result like the right side of this image:
However, I would like to make it look like the one on the left using our function if possible.
Thank you for your response.
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Moving/Rotating a placed shape later on
Hello,
Assuming that we are using SKILL commands to draw several shapes. Is there any way to shift and/or rotate them?
Currently, as we place the shapes (e.g. to form a transistor), all the shapes are independent of each other and it is very hard to move/rotate them all together.
It will be very nice to know if we can perform those actions as well.
Thank you.
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[skill code] Changing layer name
Hi
I tried to change layer name from "Top" to "M1" using skill function.
layer dbid->name = "M1" .. this code return read only error.. is there any fuction for this?
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PVS - Cadence Physical Verification System
Hi all,
Please can you give us the advice how can we integrate PVS into virtuoso environment? We install it, but PVS menu dont appear in virtuoso layout menu. Does it some variables setting? thank a lot
Martin
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Warnings Creating a Netlist
Hello i'm trying to make a PCB desing using the Cadence OrCAD Release 16.3, when i finish doing my schematic on Capture, and i try to create a netlist, there is a warning message that refers me to the "netrev.lst" file, i open it and there are this 2 errors:
#1 WARNING(SPMHNI-192): Device/Symbol check warning detected.
WARNING(SPMHNI-194): Symbol 'TSOT23-5' for device 'TLV70025DDCT_TSOT23-5_DBV5' not found in PSMPATH or must be "dbdoctor"ed.
#2 WARNING(SPMHNI-192): Device/Symbol check warning detected.
WARNING(SPMHNI-194): Symbol 'PAG64' for device 'ADS1298_PAG64_ADS1298' not found in PSMPATH or must be "dbdoctor"ed
I'm using some .dra, .psm and .pad files, that i downloaded from texas instrument webpage, when i finish connecting the circuit i change the PCB FOOTPRINT on the cadence caracteristics of each device, but when i try to place the parts on the PCB Editor, there is First: no preview, and Second: there is not part to place.
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Clock Tree Synthesis of a delay chain (tapped delay line)
In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist.
If this netlist is used, during Clock Tree Synthesis (CTS) stage, the tool (SoC Encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. If delete clock tree option is removed and CTS is run again, it comes out with a message that the clock has already been built and will not move forward.
I tried making the input of the delay chain as a leaf pin, which enables me to route the initial part of the clock. However, since I defined it as a leaf pin, it does not trace it further and the output of the delay chain is not built as a clock tree.
Any idea as to how to proceed with CTS for this? Do I need to specify anything specifically in the ctstch file?
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[SOLVED]: IC615 installation?
Previously the installation package was based on CDROMs and we normally point to CDROM1 in the InstallScape to start installation. But for the one I downloaded have not found any CDROM folder.
The list of folders and files in the download are:
1. iscape_logs (folder)
2. kits (folder containing lots of t.Z files)
3. .kpsource (file)
4. Hotfix_IC06.15.xxx-615_lnx86.sdp (file)
and
5. ic_index.sdx (file)
The MMSIM12 also has similar files and folders. The installation procedure changed or am I missing something? Where is the base package?
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Getting libraries and footprints from a PCB Editor file for use in the original OrCAD Capture file.
I'm quite new to OrCAD and all the software packages, and so have a very low understanding of things while I'm trying to learn.
My problem is that I have an exisiting Capture file that I would like to update, add parts to, and export to the PCB Editor. The capture file has several issues when trying to make a netlist because the file I was given refers to places on disks and in memory that I don't have access to. I have the original PCB file made from the original Capture file and have been trying to work backwards to get the information needed for Capture (footprints & libraries).
I used File>Export Libraies in the PCB Editor which dumped the libraries and left them in a directory. These files have.txt .dra .pad .psn and .fsm extensions. I've done some searching to see how some of these files are used in storing the physical information about the parts they describe, but I'm sure I don't understand it completely yet.
Ultimately, my question is how, if it's possible, do I use those .dra et. al files to allow Capture to understand the components in the schematic so that it can make a usable netlist to export to the Editor.
The exact error I'm getting is that, for a good number of parts, the associated files are "not found in PSMPATH or must be "dbdoctor"ed".
I apologize in advance for my simplistic level of understanding and thank you for taking the time to try to help me.
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Drawing the silkscreen oulines the width of the shape can be increased?
Hi.
I had created the footprint and then i had tried to put the shape outline for that, i want to increase the shape outline width it is possible from 0.127mm to 0.254mm. Is there any option to increase the width of it.
Thanks & Regards.
Dhamodharan
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Design rules for library TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block)
Hello all,
Normally the thumb rule followed in the 0.6u technology for the difusion length of an NMOS transistor is 3um+gate length. What is the thumb rule followed for diffusion length in TSMC 0.18u?
I am new to drawing of layouts using the TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block). previously i had been using 0.6u technology. where can i find the design rules for this TSMC 0.18u.
Please help me.
Thanks in advance
Normally the thumb rule followed in the 0.6u technology for the difusion length of an NMOS transistor is 3um+gate length. What is the thumb rule followed for diffusion length in TSMC 0.18u?
I am new to drawing of layouts using the TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block). previously i had been using 0.6u technology. where can i find the design rules for this TSMC 0.18u.
Please help me.
Thanks in advance
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netlist formatter for spectre and AMS
Hi Andrew,
I pray you'll find this and find the time to respond.
I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).
What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products. In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.
The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them. Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.
Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?
I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition. Is there a similarily simple way to modify these as well?
Thank you in advace for any hint and help.
Kind Regards,
Jörg
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