I have two redundant cores which are synthesised differently. Now after routing i have to extract the similar nets from both cores and find out whether these nets are overlapping or not. As both of the cores synthesised differently so its difficult to extract nets by name.
can any one help me out in sorting this issue?
I have a top level verilog testbench instantiating an analog spectre module (subckt). I can run a transient simulation with the Incissive irun flow but I could not figure out how to do the following:
- sample an internal voltage/current in the analog module and use that in the verilog code to make a decision:
if ( V(I0.I0.I0.analog_node) > 1 )
// startup is done
- set the voltage on an internal analog node from the verilog code.
- specify the simulation end time from verilog only. I have a $finish statement in verilog but the simulation does not run without a tran statement in the analog code. For now I just made the tstop paratemeter for the tran statement very large so the $finish gets called much earlier, but I'm wondering if there is a better way.
Any help is appreciated.
Hi.
Could anyone help about plot setup in Allegro PCB on linux platform.
I have CUPS-PDF virtual and some another printers in my linux box.
How I can use it for plotting from Allegro PCB on linux platform?
How I can make color plot from Allegro PCB on linux platform?
Do I need to create my own aplot.stipples file for perform color plot from Allegro PCB on linux platform?
Thank you.
Is there any way to change/define default settings for ViVa waveform viewer? I usually start my simulations with a script instead of directly via ADE-L and view the results using the standalone ViVa viewer.
As I typically want to save the plots for embedding in reports, I need to make the traces fatter ("bold") which is very painful if one has to do it by hand for all the curves.
How can I change this so that the traces are plotted bold by default? I'd also be glad to know what other settings I can modify at ViVa startup.
Thanks,
Vivek
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Hi Andrew,
I have problems in performing the “OverUnder” operation (=first using dbLayerSize with a positive amount, then with a twice the same negative amount, then with the positive amount again) caused by the fact that polygons cannot have more than 4000 points in SKILL. The purpose of the OverUnder operation is to remove acute angles, too small minimum spacings, and too small features during data preparation. These would create DRC errors.
I am designing photonic components, therefore the typical size of my cells is 10um x 10um or larger, moreover I have to use orthogonal polygons, and the curves are snapped to a 1nm grid.
I have a routine that writes such large polygons as a sum of subpolygons, each having less than 4000 points.
When I apply the dbLayerSize function to all the subpolygons at the same time, Cadence crashes –I assume because all the subpolygons together have more than 4000 points.
I ended up therefore by applying the dbLayerSize operation to single pairs of neighboring subpolygon, one at the time. The problem is that the result of the OverUnder operation depends on the way the big original shape is split into subpolygons. This is clearly not a clean solution, and I discarded it. Also, it is quite slow (taking few minutes for a single layer).
As a second attempt, I tiled the big polygon (=union of the many subpolygons) using square tiles (I used to this end the dbLayerAndNot) and applied OverUnder to each of them separately. Once this was done, I repeated the operation with the dual square lattice obtained by translating the tiles by half the tile pitch in both x and y directions. The result is predictable (as far as the tile size is sufficient), but the algorithm is extremely slow because of the dbLayerAndNot operation.
I wonder if there is a known solution to this problem.
For example, is there a way to get rid of the 4000 vertices per polygon limitation?
It would be great if I handn’t to go outside the Skill environment (e.g. by using Calibre), since these pCells see a number of other post-processing steps in Skill.
Thanks a lot in advance,
Dear
I want to automate the synthesis of 100 IP cores so i wrote a small script (see below),
but i am stuck on <rc>
In easy way, rc seems does not like be called in a shallscript
To make it works i need get in each folder, call the rc and then run <souce synth.tcl>
Please anyone know how can i by pass the problem ?
Thank you so much
foreach i(*.C)
cd $i
rc
source synth.tcl
cd ..
end
Hi,
Ok, I am just an administrator. One of my users is adking me, why spectre gets invoked from 32bit directory instead of 64bit.
Here is the log snippet,
Memory available: 187.1503 MB physical: 5.8504 GB
CPU(1 of 4): CPU 0 Intel(R) Xeon(R) CPU E5405 @ 2.00GHz 1995.000MHz
Simulating `input.scs' on yamdrok at 12:56:57 PM, Thur Jan 27, 2011 (process id: 32263).
Command line:
/analog/cadence/mmsim71/tools.lnx86/spectre/bin/32bit/spectre \
input.scs +escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre0_31221_4 -format sst2 -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 32263
System is 4 processor, model name : Intel(R) Xeon(R) CPU E5405 @ 2.00GHz
OS also is 64 bit linux, Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator version 7.1.0.060.isr4 -- 25 Mar 2009
If you need any other i/p let me know. Thank you.
Hi,
I am trying to check if a given file exists in one of the directories listed in the parent of parent of current directory (2 levels up)
Code:
isFileName(ruleFile list("..." ) )
This doesnt seem to be correct.
Could you please suggest a solution for the same. Is there an alternate to varying the SKILL Path?
Thanks,
Bindu
Hello Experts,
I was designing a 2x4 decoder for my use in the implementation of FPGA
CLB. when i try to simulate the decoder circuit using the cadence ADE i
am getting errors as below. I am also attaching my schematic and the circuit(created by importing the
symbol and adding the voltage sources) i used for the simulation.
Please help me I am stuck.
WARNING (OSSHNL-117): Ignoring switch view 'schematic' of cell 'gnd' in library 'basic', as it does not contain
any instance. To netlist this cell, add this switch view to the stop list or to
ignore any specific instance set the property 'nlAction' to value "ignore" on
this cell view.
WARNING (OSSHNL-117): Ignoring switch view 'schematic' of cell 'vdd' in library 'basic', as it does not contain
any instance. To netlist this cell, add this switch view to the stop list or to
ignore any specific instance set the property 'nlAction' to value "ignore" on
this cell view.
WARNING (OSSHNL-160): The primitive, 'NCSU_Analog_Parts/vdc/spectre', was not used in the last netlisting session in this
current run directory. Therefore, re-netlisting all cell views where this
primitive is instantiated.
Netlist Warning: The netlisting procedure specified for (NCSU_Digital_Parts nfet spectre) is
obsolete. You can convert your library with the
Tools - Conversion Tool Box menu on the CIW.
*Error* ilGetString: arg must be symbol or string - progn(bn)
*Error* ilGetString: arg must be symbol or string - progn(bn)
I am using the funckey "code below" and now with v16.5 a "Assign Pattern" window is popping up. I am trying to either set the pattern or disable it completely so my "F" key is more effective.
Thanks in advance for the reply :)
funckey F "generaledit; prepopup ; pop dyn_option_select 'Selection set@:@Clear all selections' ; set prompt ; prompt 'Enter Ref Des (on next step click pattern to keep it highlighted' ; refdes $prompt ; zoom selection; hilight ;generaledit "
I've been playing around with namespaces and environments recently, and have observed the following
pros and cons:
Hi Andrew,
I pray you'll find this and find the time to respond.
I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).
What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products. In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.
The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them. Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.
Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?
I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition. Is there a similarily simple way to modify these as well?
Thank you in advace for any hint and help.
Kind Regards,
Jörg
Hi,
I have a rather large test bench in ADE-XL with many global variables. I was wondering if there was any way to reorder them, or read/write them from a file. Dragging and dropping like in ADE-L doesn't seem to be working for me. I am using version IC6.1.5-64b.500.17.
Thanks
Good day!
I want to make library that when added to schematic, the instances are not netlisted during spectre simulation.
The symbols does not have models and are designed for CDF parameter extraction only.
I have a reference LIBRARY with this property but I can not find out how it was implemented.
I tried to compare the CDF properties of the refrence and the NEW library I created and they are the same.Even having the same CDF properties, my NEW library still netlists the symbols.
Is there anyone out there who could help me with this problem?
Hi everyone,
Hopefully that i post my question in correct forum :).
I am using a script to change 45 degree's maximum length from 5 mils to 9999 mils, i have also another script to change back
from 9999 to 5.
It seems not making sense since i have to use 2 keys, so i raise up an idea that is there any way to use a key to toggle 2 commands ?
Any idea is welcome.
Thank you,
Thuong.
i'm a beginner of skill&rod, i've wrote a skill file using rod functions. how could i translate it into a layout cellview using IC5141.
thank you
Hi All,
I am running below code in batch mode. It will run DRC in batchmode. It will take 10 mins. I just want to print "completed" in CIW once it is done.
How can I know task is completed or in progress once it is entered into batch mode. ipcGetExitStatus(cid) is there but is giving current status only.
TMPVAR = buildString(list("perl" " " "strOut.pl" " " cv~>cellName " "
cv~>libName " " cv~>viewName " " ) "")
printf(
"****************************************************************** \n
**************************RUNNING ViaRedunDency ***************************** \n
*******************************************************************"
)
cid=ipcBeginProcess(TMPVAR "" nil nil nil "ls.log")
ipcActivateBatch(cid)
ipcActivateMessages(cid)
Thank you,
Chandaka.
i am unable to get expected output for forward converter circuit of attached doc, becoz of transformer modeling(2 primaries and 1secodary) can anyone help me to model the transfomer.
I tried to create model from pspice modelling app available in latest release but iam not getting output,thank you in advance.