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problem using CDL in to import a spice netlist ?

July 6, 2011, 2:29 pm
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Hi All,

I am using " CDL->Import " to import a spice netlist in order to create a corresponding schematic and make some simulations.

 When I import the .spi file with or without any DeviceMap file, MOS devices are imported in the schematic, but not diodes and  resistors. Aslo, the importation doesn't differenciate 3.3V MOS (3Vnfet, 3Vpfet) devices from 1.8V MOS (nfet, pfet) devices. How to differentiate them?

Any help will be very appreciated.

here are the related files:

 ******************************
SpiceFile : Example.spi
*******************************

.GLOBAL VDD VSS VD33

.SUBCKT EXAMPLE OUT IN
M_0 NET_1 IN VSS VSS N W=33U L=0.4U
M_2 OUT NET_1 VSS VSS ND W=22U L=0.3U
M_1 NET_1 IN VDD VDD P W=30U L=1U
M_3 OUT NET_1 VD33 VD33 PD W=44U L=2U
D_0 OUT VSS DB AREA=613.134P
D_1 VD33 OUT DP AREA=161.84P
D_3 VSS VD33 D1 AREA=590.4P
R_0 VDD NET_1 1221.24
R_1 NET_1 VSS 656.98
*PGATE NGATE
.ENDS EXAMPLE

 ******************************
DeviceMap File :
*******************************

devMap := nfet N
propMatch := subtype NM
termMap := D D G G S S B B
propMap := W W L L
addProp := model nch

devMap := nfet ND
propMatch := subtype NV
termMap := D D G G S S B B
propMap := W W L L
addProp := model nch3

devMap := pfet P
propMatch := subtype PM
termMap := D D G G S S B B
propMap := W W L L
addProp := model pch

devMap := pfet PD
propMatch := subtype PV
termMap := D D G G S S B B
propMap := W W L L
addProp := model pch3

devMap := diode DB
termMap := PLUS PLUS MINUS MINUS

devMap := diode DP
termMap := PLUS PLUS MINUS MINUS

devMap := diode DN
termMap := PLUS PLUS MINUS MINUS

devMap := diode D1
termMap := PLUS PLUS MINUS MINUS

devMap := resistor RES
propMatch := r 1221.24
termMap := PLUS PLUS MINUS MINUS

devMap := resistor RES
propMatch := r 656.987
termMap := PLUS PLUS MINUS MINUS

******************************
log File : ni.log
*******************************

 ##########################

Reference Libraries...
cmosp18
tpz973gv_280a
##########################
---- Device-mapping enabled ----


1 subckt(s) found in the netlist file.


==========================
 Subckt: EXAMPLE
==========================

Created the CV EXAMPLE->netlist_tmp.

#####################################
 MOS Instance: M_3
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview pfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview pfet->symbol.

instName->'M_3' is created.
The net 'OUT' of instance 'M_3' has been connected to the terminal 'D'.
The net 'NET_1' of instance 'M_3' has been connected to the terminal 'G'.
The net 'VD33' of instance 'M_3' has been connected to the terminal 'S'.
The net 'VD33' of instance 'M_3' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_1
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview pfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview pfet->symbol.

instName->'M_1' is created.
The net 'NET_1' of instance 'M_1' has been connected to the terminal 'D'.
The net 'IN' of instance 'M_1' has been connected to the terminal 'G'.
The net 'VDD' of instance 'M_1' has been connected to the terminal 'S'.
The net 'VDD' of instance 'M_1' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_2
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview nfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview nfet->symbol.

instName->'M_2' is created.
The net 'OUT' of instance 'M_2' has been connected to the terminal 'D'.
The net 'NET_1' of instance 'M_2' has been connected to the terminal 'G'.
The net 'VSS' of instance 'M_2' has been connected to the terminal 'S'.
The net 'VSS' of instance 'M_2' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_0
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview nfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview nfet->symbol.

instName->'M_0' is created.
The net 'NET_1' of instance 'M_0' has been connected to the terminal 'D'.
The net 'IN' of instance 'M_0' has been connected to the terminal 'G'.
The net 'VSS' of instance 'M_0' has been connected to the terminal 'S'.
The net 'VSS' of instance 'M_0' has been connected to the terminal 'B'.
INFO (CDLIN-54): CDL In successfully created the schematic view tpz973gv_280a.EXAMPLE::netlist. Read the log file
'conn2sch_EXAMPLE.log' for more information.
 
  TOTAL CELLS #: 1

       *************************    
       ******   SUMMARY   ******    
       *************************    

    CELL                           TERMINAL #    NET #      INSTANCE #   
  -----------------------------------------------------------------------------
    EXAMPLE                          4             6          4       

********************************************************************************************************************************************

Even if I change the original resistor description R_0 VDD NET_1 1221.24 to R_0 VDD NET_1 RES r=1221.24 the problem is still the same for resistor importation.

 Thanks for your support !!!

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Need help on forward body biasing and CSAFF&CHLFF circuit

December 11, 2012, 6:53 pm
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 Hi fellow members!

i need help on the topic of forward body biasing.

I am currently using the 65nm process with a wp/wn ratio of 240/120 which is 2.

In regards to the body of the pmos and nmos, i normally tie them to VDD and GND respectively. However, coming upon the topic of forward body biasing i am quite confused as to how should i implement the technique? Could anyone help me out? Thanks! :)

i realize in some circuits, simply apply a "0" to the pmos body and this provides FBB. Dont seem to understand why though.

Would appreciate any form of help.

Does anyone has experience with CSAFF and CHLFF circuits? need help too.. complementary sense amplifier flipflop and complementary hybrid latch flipflop.

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extract memory value in systemC

December 11, 2012, 7:43 pm
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Hi all,

 I have 2 files. 

In file A.vhd, I model a memory using "type t_mem is array(conv_integer(BASE) to conv_integer(TOP-1)) of std_logic_vector(7 downto 0);     variable mem : t_mem;".

In file B.cpp, I use "rtl_mem_value.observe_foreign_signal(memory_path)" to extract memory value, but I get "ncsim: *W,SCOOMR: Expecting port, signal, or net for out-of-module connection".

 Can anyone tell me how I can extract memory values?

Thanks

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Is that a way to set exclude particular layers (different purpose) from carry connectivivy

December 11, 2012, 8:52 pm
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Hi Guru,

I owned a techfile where define M1 with purpose of drawing, PH and SW. (Info:PH is for place holder and SW is for switch). How can i set that only M1;drawing carry the connectivity but other won't.

 I tried to manipulated the interconnect validLayers setting but failed, M1;PH still carry connectivity when connected with M1;drawing. Any best way to tackle this issue. Thanks

  ( "virtuosoDefaultExtractorSetup" nil
    interconnect(            
        ( validLayers   
            (                 
                (M1 drawing)                              
                (VIA1 drawing)
                (M2 drawing)
                (VIA2 drawing)
                (M3 drawing)

                ..................)))

 

 My intension is simple, im looking a way to set that ONLY M1;drawing carry connectivity, the layer with other purposes are ignore.

Thanks in advance. =)

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Subtraction Between two layers?

December 11, 2012, 8:27 am
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 Hi,

I just started cadence couple of days back for designing my patterns, I wanted to subtract two layers and already wrote a code but not sure its a right one or not. Could anyone help me please and let me know is this a right on or not,

 load("/usr/cdscad/libw/utils/rectw.il")


procedure( subtraction( @optional origin ww tlength outlayer)
(prog (xx yy np xo yo lw)

   subl1 = nil
   subl2 = nil

   xo = xCoord(origin)
   yo = yCoord(origin)
   


;; Draw First rect Layer

   xx = xo
   yy = yo-ww/2.0
   r = rectw(xx yy tlength ww "metal1")
 subl1 = append(subl1, list(r))

;; Draw Second rect Layer

   xx = xo
   yy = yo-ww/2.0
   r = rectw(xx yy tlength ww "metal2")
  subl2 = append(subl2, list(r))

dbLayerAndNot((getEditRep) outlayer subl1 subl2)

)

)

 

Thanks

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Backdrilling manufacturing process

September 28, 2011, 7:37 am
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Does anyone have details how a a backdrilled board is finished? In other words, what ends up in the hole? Depeneding on when it happens in the entire process, it seems unlikely that leaving exposed copper in a via hole is a good idea.

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Kitchens Sheffield

December 11, 2012, 11:39 pm
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 Kitchens Sheffield. Kitchens Sheffield. www.solidwoodkitchen.co.uk . £ 595 full kitchen with appliances. Cheapest kitchens in Sheffield. TEL 01616-694785. Kitchens Sheffield

 

 

Kitchens Sheffield

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Reg: OFFSET GRID MOVEMENT OF PARTS IN ALLEGRO16.6

December 11, 2012, 11:59 pm
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Hi,
In Allegro 16.6 while moving components its not jumping between grids giving smooth movement regardless of grid then after placing quickly
aligning to near by grid . Is there any setting I need to do for movement of components as it was in 16.3 ?
eg for more clarity : I have set 39.37mil grid to place same pith BGA ,but while moving BGA , its pad not picking grids showing smooth offset grid movement
Regards,
Girish Kumar
P Go Green! Think Before You Print This Email.
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3d model

December 11, 2012, 4:53 am
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how to attached 3d files (.step et c) into the cadence library file or  how to attach 3d files to the compoenents so that we can review the placment  3d mode ?

 

Rgds,

Bala R

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how to determine some cellview is editing by somebody else?

December 11, 2012, 6:56 pm
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Hi... This is Alvin Park. SKILL Beginner ^_^

 

I programmed a SKILL code for auto editing.

first DB open by "dbOpenCellViewByType"

 TDB = dbOpenCellViewByType( LibName CellName "layout" "masklayout" "a")

in case normal... this return correct DB code to TDB parameter. So far so good.

 

but in case of editing by somebody else (locked) , CIW shows warning that this cell is locked. (shows warning only!)

This code return correct DB code in spit of not editing the cell.  

 

So before DB open by editing mode,

How can I determine some cell is editing by sombody else?

 

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schematics don't fit on board, design improvement needed

December 12, 2012, 2:41 am
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today my pcb maker told me they can't get all components on the board. I was wondering if some might have suggestions for improvement. Attached the schematics and pcb design. the part outside the white lines does not fit on the board. pcb size is 15x8mm. Total available space for pcba is 15x8x6mm. i appreciate your help.

 

 

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String returned from axlDMFileBrowse()

December 9, 2012, 9:31 am
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 Hi All,

Would you please kindly point out what did I do wrong in few lines of code below?

My objective is to acquire file name of browser, pass it to IDF_IN fuction. My variable
"file_name" is recongized by axlUIViewFileCreate() function but is not recognized
by axlRunBatchDBProgram(....-d PTC) option. How should I handle that variable?

Any effort is much appreciated.

   procedure(view_file()
   let( (emn_file file_name idf_result cur_db)
     file_name = axlDMFileBrowse(nil nil ?optFilters "MCAD file (*.emn)|*.emn")
     axlRunBatchDBProgram("My IDF in" "idf_in -o %s
                                          -d PTC file_name"
                                          ?reloadDB t)
     axlUIViewFileCreate(file_name "My EMN file" nil)
   )) ; end let, end procedure my IDF in 

Thanks in advcance,
Vinh Ta

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Geometric wire options (VLE)

December 13, 2012, 12:47 am
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How can I set min. num. of cuts, wire width per metal, use of square collinear vias and other options for geometric wire without starting VXL, making my own contraint and setting it for default.

I assume that the geometric wire has the same properties (or most of them) as the "real" wire. 

Is this a bug or a feature? Since in Virtuoso L there is no Wire Asissitant to set all these options (IC6.1.5 ISR13).

Thanks

 

 

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a weird problem about calculator of cadence ic5141

December 12, 2012, 8:54 am
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Normally when I call out the Calculator from the ADE,a window with functions will display.but recently,a weird problem occurded,the founctions in the window disappear,as you can see the picture in the attachment below.Can anybody explain why?
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axlCNSCreate for Same net constraints

December 12, 2012, 11:09 am
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Hi all,

I'm trying to create a same net spacing constraints using axlCNSCreate command, but I only see the option for 'physical, 'spacing, and  'electrical option on algroskill.pdf.  

Am I using the wrong command or just not looking at the right document for this?

Any help will be much appreciated. 

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attach label to a pin as a 'children'

December 12, 2012, 7:49 am
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Dear all,

 I have only pins in the layout and I want to attach a label to it. Unfortunatelly the 'children' cannot be set.

Anyone knows how to set it correctly?

Here is the example of my code. 

Regards,

 

Normal 0 21 false false false FR X-NONE X-NONE MicrosoftInternetExplorer4

/* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tableau Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;}

cv=geGetWindowCellView()
p=caar(cv~>terminals~>pins)
foreach(p cv~>terminals~>pins
p1=car(p)
p1~>net~>name
f1=car(p1~>figs)
unless(f1~>children f1~>children=
dbCreateLabel(cv list(f1~>layerName  "label" ) centerBox(f1~>bBox)
p1~>net~>name "centerLeft""R0""roman" 0.5)))
 
 
*Error* setSGq: (DB-370034): dbSetq: Cannot set attribute - children
 

 

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Program Skill Development

December 4, 2012, 3:04 am
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 Hi all,
 
 I have to realize a project about PCB. To do this I have to use SKILL language. 
 
 My subject: I have to write a SKILL program which automatizes the creation of text block. In fact I have to use a library to take PCB dimension, and text block format (A4, A3, ...). Then I write a script which calls many functions to do that.
 Well the text block need to be fill with information of PCB (Client name, no Pb in the PCB, Date, name of responsible, etc...). Informations are present in text files, So I have to take them, put in text blocks, select format of text block, and then, generate the Gerber files.
 
 Anyone could help me please.
 
 English is not my native language, so please ask me for more information. It's very important for me and urgent.
 
 Thanks
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OrCAD Capture 16.5 Start Page

November 15, 2011, 11:04 am
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I just updated to v16.5 and the new Start Page/Getting Started screen is driving me nuts needing to close it every time I open a design.  How can this be disabled?

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add aggressor info on nets

December 13, 2012, 3:35 am
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 i am trying to do a crosstalk analysis for group of nets...using sigxp which is bundled in OrCAD PCB Pro-16.6. now i would like to assign the aggressor info to the nets of my board. How can i assign aggressor/victim details to the nets on board

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licence requirment for Analog Autoplacer

December 13, 2012, 3:55 am
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Hi,

When I run autoplacement in virtuoso VLS-GXL I get following errors  p, li { white-space: pre-wrap; }

Analog Autoplacer unable to checkout license/tokens sufficient to run. Check that you have sufficient licenses and are in VLS-GXL

 

 

 

 

 

what could be the solution.

 

Regards

waseem

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