How to change the thickness of wire?
How to change the thickness of wire, in PCB Designer? I am using Cadence 16.5, and I know how to change the wire width, just wondering how to change the depth or thickness of the wire~
View ArticleHow to add a mark?
Hi Experts, We can see a mark, square with cross, to know a point on measure.I want to add the mark in my skill.How to add the mark?Thanks in advance.
View ArticleHow to stream-out gds with via/pcell name get renamed with prefix only
Hi.Is there a way we can stream-out a cell and renamed only the via and pcell with prefixes? Currently virtuoso only allow us to rename the cell with prefix/suffix. Can we add prefix/suffix only for...
View Articleabout stability (kf,b1f) simulation for mixer
Dear All,I would like to know whether we can use the sp or (psp or hbsp) to simulate the stability (kf, b1f) performance for a circuit like mixer (or Tx or Rx).K factor (kf) and b1f are used to check...
View ArticleDRC Fixing in Encounter
Hello Ive been trying to do some DRC fixing in Cadence Ecounter. The basic problem I am facing is offgrid/nogrid routing errors. I tried setting the routeOngrid option true and routed the design...
View ArticleAllegro 3D-Viewer Bottom Component View not correct
When executing the 3D command in Allegro PCB Designer 16.6, the top components are placed correctly with the smt leads flush on the top conductor surface. However, if I rotate the design from within...
View ArticleIssue in "spectrum" function of Cadence
Hi All,While calculating the SNR,ENOB using the "spectrum" function in calculator,I seem to be getting rather erroneous results. As seen in the attachment, I am getting "-1.9 bits" as my resolution...
View Articleverilogin problem: modules are imported twice
Hi All,I'm importing some verilog files into dfII library to generate a schematic to run a transistor level simulation.The library for standard cells are created first. When I use verilogin, it can...
View Articleimporting EDIF file (library install)
Hi, I've been trying to install some io libraries into virtuoso 6.1.5 and having little success. It's the CIO220_3.3V_Compact_Inline_I_O_(0.18um)_2003.12 library I'm trying to install at present, I...
View ArticleDoes the Capture support the chinese font in tcl/tk program?
when I load a tcl/tk program into capture. there are some chinese font couldn't print out.how to solve this problem??tks!
View Articletwo dimensional bus notation in schematics
I have a circuit block with a bit array input, CB<2:0>I use a 62-element array of this block in a schematic.How should i name the resulting two-dimensional input.I tried the following and none of...
View Articleoperating points implementation (verilogA and CDF)
Hello, I am developping a verilog A model (with 2 sections analysis("tran") & analysis("dc")), with multiples internal variables declared whith 'real' statment in verilogA code.real...
View ArticleHow to put the Multilayer board in Layout 16
Hi, I had drawn the schematic and trying to put 4 layer board.What should i have to do? Suggestions of the four layer board.
View ArticleHow to create a layout from 2 circuits (2 .max files)
Hello,First, I'm new in the community so I don't know if it's the best place to make this question. The question is that I want to make one layout design from 2 different pcb (.max files). I have 2 PCB...
View Article*Error* _hiExportImage: Unable to allocate image of size (1010851,1621501)
Hi,I was trying to export layout view into a .bnp file using skill function : Lib="TEST_lib"cellname="TEST_CELL"wi=geOpen( ?lib Lib ?cell cellname ?view "layout" ?viewType "maskLayout" ?mode...
View Articlesaving ams config hierarchy
let us say I have a testbench running ams. There is a cell in there called pll_top. It is very complex and deep. As such I have a particular set of views instantiated all the way in the tree. Once...
View Articleskill to plot waveform contained in a file into w-viewer (could be VIVA)
Posting in the hope that someone has a function they can share that will take a file (two columns of x, y data) and plot that in the active graph window.Probably leverages this solution from CCS :How...
View ArticleHow to set the model parameter STIMOD in simulation?
Hi The STIMOD is the LOD stress effect model selector. I can view this after any simulation by printing the model parameter in virtuoso ADE. But I have checked the modelfile.scs which is included in...
View ArticleIs there a way to print model parameter using Hspice-D version2012.03 after...
Based on my knowledge, I use Spectre simulator and after simulation, through Results=> Print Tab, I could print model parameter. While in Hspice is there a similar trick to do this? Any reply is...
View ArticleSimCompare - ignore time - compare only values
In SimCompare, is it possible to compare only the trace values and ignore the timestamps?For example, given the two traces of the same signal but at RTL and SystemCSystemC: 7@10ns , 10@20ns 10,...
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