Hello,
I am developping a verilog A model (with 2 sections analysis("tran") & analysis("dc")), with multiples internal variables declared whith 'real' statment in verilogA code.
real x1,x2,x3,x4,x5;
In the CDF, I declare only X1 and X2 as operating points, and sometimes in ADE all the varialbes (X1 --> x5) are reported.
Why?
Regards,
Fab