off-grid vias
I am using Orcad Layout 9.0 and am getting alot of off-grid via errors. I have changed the grid several times with no sucess. I am trying to route to a footprint that has 1mm pitch. Please advise.
View ArticleChanging spacing constraints when opening Allegro
Hi All, I was wondering if anyone can guide me in the right direction.I'm trying to make it so I can set the bottom SMD pin to TH distance when allegro starts up. This will need to be done to all...
View ArticleSynthesis in rclabs using slow and fast library
Hi good morning all, i have written a code for inverter chain and synthesized using slow and fast lib sepaerately,which represents slow path and fast path helpful in timing...
View ArticleRTL Compiler, Min Libraries and CPF
Hi,For synthesis (RTL compiler) I define a worst case libraries read_cpf -libraries, and in the CPF I usedefine_library_set -name my_lib_set _librares {libA_slow.lib libB_slow.lib libC_worst.lib} i.e....
View ArticlePHASE_TOLERENCE?
Hi all, why we have adjust the phase tolerence between D+ and D-?what is the difference between static and dynamic phase tolerence?Anyone please guide me., Regards,Karthik.
View ArticleAddition of Noise file to input voltage source of Cadence Spetcre
Hi., I am facing problem in adding noise in transient analysis in cadence spectre .Can help me how to add noise as input source for transient analysis using simulator cadence spectre .
View Articlecreate the multiple instance in parallel
Hi all, i draw a sub-circuit, and i would like it to be a sybmol, so that i can implement it in the top level circuit, so my question is how can i create a multiple "self design symbol" in parallel but...
View ArticleHow to know if a terminal pin is in the left,right,top and bottom of a...
Hi All,How can I know if a terminal pin is in the left,right,top and bottom of a circuit symbol? and how to count them?ex.left - 13 terminal pinright - 10 terminal pintop - 2 terminal pinbottom - 0...
View ArticleSchematic p-cell for modelling parasitic resistance and capacitance
Hi, I'm looking for a schematic p-cell which models parasitic resistance and capacitance in layout.A former employer of mine had this function; to model a metal wire or interconnect in the layout,...
View Articlea question about cell characterization
how does ELC examine the syntax of input netlist?
View ArticleHow to view adexl in GUI mode?
Hi All,I' am running ocean XL in batch mode. I use ocnxlSaveSetupAs function to create the adexl view. Here's the context using the function:ocnxlSaveSetupAs("myLib" "myCell" "adexl")My runs are...
View ArticleaxlSingleSelectPoint not accurately !
Hi all! I'm writting a skill to check at start point & end point of a cline if pin exist or not, if pin exist and pin's netname ="dummy", then assign that cline to that pin. AND , if the...
View ArticleRun Skill Scripts and Update Schematics from Unix Command Line
Can we load and run skill procedures without having to invoke interactive command window. I have started to read about "interprocess communication" but it looks like these need to be run from the CIW...
View Article[PCB Designer] Shape toolbar
Hi all, When I select the shape toolbar under PCB Designer, I only have the "delete island" button on it. How could I show the other buttons ?Many thanks for your help and kind regards,
View Articlelatest Specman-Matlab package
Attached is the latest revision of the venerable Specman-Matlab package (Lead Application Engineer Jangook Lee is the latest to have refreshed it for a customer in Asia to support 64 bit mode. Look...
View Articleimport cdl file in schematic
I would like to import cdl file but i have problem. What is the map file? How I can to import cdl file?
View ArticleGenerating Reports
Hi,Where can i see what are the most important reports to generate after each step? (floorplan/placement/cts/routing/post rout)Thanks!
View ArticleTeaming up on a Design
I'm looking for some guidance on the following. A co-worker and I have teamed up on a fairly intense 12 layer design (controlled impedance, DDR, tuned traces, 684 ball BGA, etc) My partner is...
View ArticleReg .VCD file generation
Hi, I need to run power analysis . so i need .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd...
View ArticleHelp and apologies...
First, apologies if this is in the wrong area... Question. I am attemtping to follow the online tutorials for the creation of component symbols and importing a csv file of a component i wish to create....
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