Schematic p-cell for modelling parasitic resistance and capacitance

Hi, 

I'm looking for a schematic p-cell which models parasitic resistance and capacitance in layout.

A former employer of mine had this function; to model a metal wire or interconnect in the layout, you'd place a special p-cell in your schematic, enter in which metal layer it was placed, add length and width as well as surrounding density, and the p-cell would pop out with a calculated RC value and act as a lumped resistor and capacitor. This was incredibly efficient in pre-layout simulation of routing-sensitive modules.

Is there built-in support in Cadence for such a function, or will I have to write a p-cell from scratch myself? 

Best regards, 

Tore