Cross function
cross(deriv(IDC("M1/D"))) ymax(deriv(IDC("M1/D"))) 1 "either" nil nil)i.e. cross(deriv(some current))) ymax(deriv(some current))) 1 "either" nil nil)The plot is for derivative of current (y-axis) vs...
View ArticleaxlDBCreateSymbol issue with mechanical symbols
HiI'm seeing something really weird here, hope someone can help me out.I've created some code to place components but are seeing issues when trying to place mechanical symbolscorn.dra is a mechanical...
View ArticleREG:DATABASE BUILD IN ORCAD & ALLEGRO
Hello Friends I would like to build a closely integrated Database for schematic symbol & footprint in orcad & allegro platform .. So that the design Engineer when doing the schematic...
View ArticleComponent placement is been not get updated
Hi. I had placed the components in the board on the top of the outline. When i try to place component in side of board, selcected component is get moved over a long distance of of board.Any help for...
View ArticleTiming analysis in EDI
Hi , I am facing some problems in Timing analyis of the encounter digital implementation. I have imported my design. Configured the MMMC for typical librarries.And floorplanning, placement...
View ArticlePositioning the instances in Layout editor by using SKILL
Dear All,I am trying to place copies of an instance/object ( say a simple via ) with 'x' distance separation in X-direction.Is there any in-built feature already available in IC5141 ?Otherwise, is...
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View ArticleChange NetName
I want to change/replace the NetName in the capture design through TCL Script. So far i've been able to change the PinNames of any particular part and the names of OffPageConnectors of whole pages. I...
View ArticlePlotting gm and its harmonics in a mixer
Hi,What is the cleanest method of plotting gm and its harmonics in a transconductance mixer?
View Articleexit without saving/ quit a design skill function?
Hi all,Is anyone aware of a function that will exit out of a allegro database without saving? Basically, quit out.I want to create a test coupon on symbol, but don't need the .dra file. Thanks,Jerry
View ArticleHow to deposit simulation result into a file?
Hi, I am wondering is there a way to save an output into a file, like a .txt which it is easy to read from. Specifically, in the "Setting outputs" of Virtuoso Analog Design Environment (ADE) I have:...
View Articleextracta CONNECTIVITY takes over 1.5 hours
Hello, If I run the following command:e:\Cadence\SPB_16.6\tools\pcb\bin\extracta extracta -c -m "foo.mcm" extracta_control.txt output/conn.txt With the following as...
View ArticleDesign is tight after placing cells
Hello After placing a design all the cells are concentrated in one place, the tool takes a very long time to finish and after a lot of iterations I have geometry and shorts violations.I set the Clock...
View ArticleHow do I properly format a imported properties file into SKILL to create shapes
I wrote a simple SKILL script which pulls the properties off a shape and prints into a text file.LayerPair: ("m1" "drawing") ShapePts: ((0.0 0.0) (100.0 100.0))PropertyName: Name PropertyValue: "p3"...
View ArticleHow to import/export y0,y1...y3 layers along with tech-layers
Dear All,I have added some layers of y0,y1...y3 in my chip-layout.I exported it to create a .gds file.I then tried to import the .gds file.To that end, I created a New library. I attached the PDK...
View ArticleOracle 11g Online Training
Oracle 11g Online Training offered by bytes Online Training.Our Oracle 11g online trainers are very good experience in this relavent field.Oracle 11g online training is the best online training in...
View ArticleBest of Free PCB Design Software
Best of Free PCB Design Software 1. ZenitPCB2. FreePCB3. TinyCAD4. Osmond PCB5. BSch3V6. ExpressPCB7. Kicad8. gEDA9. Fritzing10.DesignSpark PCBhttp://www.olcourse.com; http://www.teindo.com;...
View ArticlePositioning the instances in Layout editor by using SKILL
Dear All,I am trying to place copies of an instance/object ( say a simple via ) with 'x' distance separation in X-direction.Is there any in-built feature already available in IC5141 ?Otherwise, is...
View ArticleAssertion detect *WORNG* fell of line due to gated clock
Assertion detect *WORNG* fell of line due to gated clock Simulation assume line was high and on the posedge of clock the line is constant low and detect it as FELL and assertion is active due to that...
View Articledefstruct in pcell (for layout), is it possible?
Hello,This is what I want to do:Create a pcell that instantiates other pcells (layout)Perform various "measurements" on this new instance (i.e.: retrieve the bounding box)This information has to be...
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