paste size vs pad size
When using a rectangular pad, it's easy to make a paste layer a little smaller. First, is this really needeed?My bigger question:When I use acomplex shape to be the pad, do you guys just make the paste...
View Articlencsim: *E,IMPDLL: Unable to load the implicit shared object
Hi,While running simulation , i am getting the below mentioned error .Can anyone help me to fix this error.ncsim: *E,IMPDLL: Unable to load the implicit shared object.OSDLERROR:...
View ArticleOne hot assertion in RTL
Hi,What is the best way to add one hot assertion on a bus in verilog? Ex: Wire [9:0] one_hot_wire; Only one of the bit of this wire is supposed to go high in the simulation otherwise it should fail....
View ArticleFor place bound top and bottom of components solid fill ?
Hi.When i am trying to place the components in the design, place bound top & bottom the outline is get filled with solid.Whether we have to use the solid fill or any other option.Thanks &...
View ArticleProblems with IIP3 with PSS and PAC analysis
Hi I am working on a (passive like) CMOS attenuator and my problem is that when I do the IIP3 with PSS and PAC analysis my third harmonic is not increasing by 3dB. It is much lower. Me and my thesis...
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Slotted Through Hole for mounting appears filled instead of drilled
Hello. I am tryign to make a mechanical non-plated slotted through hole which will allow a device some 'wiggle room' while mounting it on a board. I can't seem to make the slotted through hole appear...
View ArticleLibrary part management
Hi everyone....brand new to 16.6 Pro...no CIS. I've managed to get far enough on my own with it to send some test gerbers (a few issues came up that I'll post later on) to the pcb house and they said...
View ArticleCan't place via next to pin
Hi,When I want to route some tracks of pins I can't place via just near the pin, while for neighbour pins I can do it easily. I have also defined a Power class net for both of them with pin to thru via...
View ArticleHow to instantiate models in verilog-A
Hello Everyone,I am new to the Verilog-A programming. I have a model for MOSFET switch written in verilog-a. Now I want to construct inverter by instantiating the mosfet model. How do I do this.Is the...
View ArticleShape filled and unfilled
I'm a new Allegro 16.3 PCB Editor User.. please somebody help me with the following question1) what is in general the difference of using shape instead of lines or rectangle 2) rectangle ( filled or...
View Articlestatic cmos design
Hi guys, I need help with static cmos designing. how to design a single custom static CMOS gate(only one gate delay) that implements the function (NOT (A OR B OR C) ANDD)) and draw a MOS transistor...
View Articlenetlist differences
Hello, I heard from a friend that every-time you run a design, a new netlist is created. How is this netlist different each time even if the circuit is same?
View Articleschematic view select
Hi,Suppose I have two different views for a schamtic. One for simulation and on for LVS. How to set it up in Cadence 615 scheamtic editor so that when go down hierarchy on this schematic (SHIFT + E), I...
View ArticleChanging config view within a single ADEXL test
Hi, I often use config views (set up using the Heirarchy Editor) to switch between schematic and extracted views of a circuit block during simulations. I would like to run a single ADEXL test which...
View ArticleSKILL code to detect empty cells while parsing CSV file
Hi SKILL experts,I am trying to parse a CSV file and populate this data into a hash table. The CSV file could possibly have empty cells. If any of the first 7 columns for a given row in the CSV file is...
View ArticleaxlStringCSVParse() bug. Allegro crash.
Big fat warning on using axlStringCSVParse().Passing it a string over 1024 characters will CRASH Allegro.Some folks at Cadence aren't doing proper testing. SKILL strings are not limited to that...
View ArticleExtracting Data Similar to Cross Section
Hello, I'm new to SKILL and am trying to write a program that will extract information found in the Layout Cross Section tool. I need to extract to a text file in a particular format, so I can't use...
View Articlenconc with (back)quote'd list constants
Google says: "Avoid nconc!"http://google-styleguide.googlecode.com/svn/trunk/lispguide.xml#Avoid_NCONCThey recommend to use "mappend" instead, which you could naively define this way (naive because...
View ArticleAbout the driving ability of digital circuits in spectreVerilog simulation.
Hi,The circuit is like below. And notG is just a very simple verilog "not gate", which code is like this.module (Vin,Vout);input Vin;output Vout;assign Vout=~Vin;endmodule;
View ArticleScheme vs Common Lisp style in SKILL++
While you can write your SKILL++ code like it is C, Maclisp, Scheme, or Common Lisp (or none of the above...), I've been experimenting with Common Lisp style lately.Trying to write Common Lisp style...
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