abutment and controlling S/D dropping
I am an end user layout engineer. I am not a developer of PDKs or Pcells, etc. so I am at the mercy of what is given me to use for the most part. I do develop SKILL code for automation of the layout...
View ArticleNetlist error when using Global Sources in hierarchy editor
This happens when I try to use global source in post layout simulations.The circuit under test is designed with a global source. And I believe the pin names are vdd!/gnd! because I have passed the LVS...
View ArticleChoose grid properties
I open Setup>Grid in PCB Editor. How can I choose all these Offsets and Spacings ? Bring textbooks and manuals for students.Thank you.
View ArticleStrongGroup suffix in net name
When I use VXL and gen from source, the transistor generated have weird net name assigned to its source/drain terminals. Rather than named "n1", the net name on the inst term is appended with...
View Article[ADE L/XL] Setting a skill expression to a design variable
Hi All,I couldn't find any post on this topic, and hope my next question makes sense...I have a testbench simulating both a 'tran' and a 'pss' analysis. I'd like to disable automatically some vpwl...
View ArticleCannot find nom.lib
Hello. I have the Pspice 9.1 Student Version and i copied some pspice files into my USB stick. From that point after, i have been getting this error message "Cannot find nom.lib". I have tried adding...
View ArticleParametric analysis - voltage error in the netlist
I found that when I run parametric sweep with fine voltage step, netlists are sometimes generated with wrong value. For example, when I run parametric analysis with the voltage changing from 0 to 1V...
View Articlecould not launch skillDev IDE
Hi, there.I'm currently using IC6.16.I tried to invoke skillDev IDE from the CIW window and the only message I got was:Loading skillDev.cxtbut nothing happened after that.I looked at the CDS.log and...
View ArticleK Stability factor
Hi I use SP analysis in ADE L and draw the KF (stability factor).The result is different compared to the K factor derived from any known equations (I got the equations from Pozar's book). i.e. I use...
View ArticleBulk connection of the mos
Hi I'm working for rewriting the mos bulk connection but I'm not getting how to get only bulk connection information I tried this command geGetEditCellView()~>sigNames..By this I'm getting all...
View ArticleUnplaced/Placed symbol;s in PCB EDITOR
I have loaded an netlist in the PCB editor and since the symbols are not placed I cannot see any of the symbols. I know they are there since Place/Manual shows all the reference designators. Why can't...
View ArticleVirtuoso Editor Tools Menu
When I first click on the "Tools" menu in the Virtuoso Schematic/Layout editor the entire Cadence GUI freezes for up to 30 seconds. This does not happen on any subsequent times I click on the Tools...
View ArticleKitchens Cabinets London
Normal 0 false false false IN X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes;...
View ArticleModifying an extracted view for post layout simulation.
I am using IC 5.1.41 and Calibre 2010.4. I have an extracted view which is extracted by Calibre and I want to use it for post-layout simulation. When I modify the extracted view, Analog environment...
View ArticleAssura Layout extract.rul debug
I am writing extract.rul for a IC technology and I am a beginner. Is there a simple way to debug while running the extraction, i.e. the visualization of the resulting layers from geomAnd and geomAndnot...
View Articleinstead of "M1 drawing" and "M1 pin layers"">Abstract Generator : abstract view with just "M1 net layer" => instead of "M1...
Hi !!I managed to get an Abstract view of my simple inverter cell, from a layout.oa view (up to M1 layer). See attachment.However, in this Abstract view, i just have one layer : M1 net. Actually I...
View Articleframes around PCB?
I do drawings of 0.5" PCBs and some 12" PCBs. I want a frame with instructions. Regardless of PCB size, I want the PCB image to mostlly fill the frame. I've been importing different sized DXFs.Is...
View ArticleHow can I preserve designators from changes?
HiIn the Orcad capture schematic environment when we try to copy a page in a project file and paste it into an another project all designators automatically changes.How can I preserve them from...
View ArticleExtracting generic devices with Assura
I would like to extract my own two terminals device from the layout.The first terminal is derived with specific derivation rules, the second terminal instead should be named according to the layout x,y...
View ArticleHow to Place Components without Dimension Information
Hello all,I'm having difficulty locating the function that will allow me to place components without dimension information about the footprint. This wouldn't be a problem if my computer isn't so slow...
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