When I use VXL and gen from source, the transistor generated have weird net name assigned to its source/drain terminals. Rather than named "n1", the net name on the inst term is appended with "_StrongGroup_#" e.g. "n1_StrongGroup_1".
FYI in the schematic I have nfet with m=16, source tied to n2, drain tied to n1. After gen from source, the nfet in layout has source term assigned to net n2, but drain term for each transistor is different: n1_StrongGroup_1, n1_StrongGroup_2, ..., n1_StrongGroup_16.
I would like to know under what circumstances would this happen, what's the purpose of these "StrongGroup" and how to deal with these weird nets. To get back the "parent" net, I could potentially do "car(net->signals)". Still, it is confusing because a net is no longer a simple net and we might need addtional queries to get back the actual net without the StrongGroup suffix.
Tried to look for documentation for this but couldn't find anything.