New VIA definition
Hi! I have to you the following questions:1) How do I define the new VIA so that I can use it later in Allegro? I know that I have to use the PAD Designer, but where I have to save the designed VIA so...
View ArticleAllegro 16.6 on windows7 invoking error
We are facing one issue when we install allegro16.6 on widows7.Once after invoking allegro it is default going to studio licence. giving an error. And we are not able to open 16.6 allegro due to this...
View ArticleWaive DRCs report
Hi All, Can I know how to generate waive DRCs report using skill? Thanks,Selva
View ArticleHow to override parameters in the same block - ADEXL Global Variables
Hello, I was wondering if you could help with the following issue:The vendor's provided model file has a definition for a parameter (param1) which I would like to override. Both definitions would...
View ArticleGetting schematic instances from multiple open schematics
Hi, I want write a skill routine that lets the user interactively select instances from multiple schematics & get those instance names. I tried geAddSelectPoint(), but that will prompt the user to...
View ArticleLayout netlist extraction
Hello,is there a simple way to extract the netlist from a layout without parasitics without doing the full LVS with Assura? I am writing the extract.rul file and searching for a way to debug it....
View ArticleRewriting the bulk connection if given mos
Please can any one help me to do this code"Code to detect PMOS and NMOS device in given schematic and change/overwrite bulk connection of PMOS to vdd! and NMOS to vss!" Here I'm struck at getting wire...
View ArticleSetting differential random data source
How can I find "differential random data generator" in Cadence? Is there such block in cadence or I have to make it by vpwl source in AnalogLib? Any suggestion will be appreciated... Regards, Hadi
View Articleassura LVS error --- No property
Hi,I am using assura for LVS check, the version is : 4.1_USR1_HF12_514There are errors like:Error (AVLVSDF-10007) :No property 'modelName' is specified for cell 'pmos'. specify property 'modelname'...
View ArticleRe:Annotate DC Operating point
Hello,After running DC simulatin, when i do Results-> Annotate-> DC operating point it is showing the following warning *Error* eval:undefined function Pls help me to fix this Thanks
View ArticleChange CDF variables from inside an Ocean script
I generated an Ocean script from Analog Design Environment | Session | Save Ocean Script. I've been able to run some simulations using this script. But my schematic has a few instances with the same...
View ArticleCDL netlisting series resistors as multiple instances
Greetings, I'm using a standard resistor model with W, L, NumSeries, and NumParallel as parameteres. All works well on the simulation side. Due to company guidelines, LVS will not combine series...
View ArticleReplicate similar rooms, copy & paste routes in Allegro PCB 16.5
Hi, I am working with 16.5. I have three similar blocks - I've defined a property "Room" for components in Schematic - in my design. I have placed and routed one block in it's Room completely. Now, I'm...
View ArticleConvergence error in Transient analysis
Actually i crated a Memristor Model by using VerilogA code. Then i designed logic gates by using the same with different methodology and i got correct simulated output but when i combined all...
View ArticleMeasuring Power Consumption in GDI based circuits
Hello,I am trying to measure total power consumption of my design based on GDI (Gate Diffusion Input) technique.I want to know that is the procedure for measuring power is same for GDI like,...
View Articlehow cadence do to calculate Z11 in a psp analysis
hi, i'm simuliting a circuit, where i connect 4 switching caps to the port, than i run a psp annalysis to get the input impedance"Z11", and i want to know how spectre do to give such result, it's for...
View ArticleHow to calculate the capacitance of a Varactor?
Two different methods give me different curves (Cap. vs DC bias voltage). However, initial value, final value and also the capacitance at zero bias voltage for both methods are the same.I use ADE L to...
View ArticleExporting s2p file from spetre
Hi,I am using IC 6.1.6 and I want to export .s2p file after s parameter simulation. I tried using sparameter analysis window>options>output parameters >filename.s2p>dtft=touchstoneBut no...
View ArticleMerging of portions of different PCB Layouts
I was just wondering, whether there's any is any way by which we can merge the portions of different pcb layouts(created using different PCB CAD Tool) and make a new PCB layout file.For e.g. I have 3...
View ArticleAvoid race condition at SPI_slave synthesis
Hello.I'm trying to synthesis SPI core, but in the simulation occurs race conditions between signals SPI_CLK and system clock (clk) in "always" block:always @(posedge clk)spi_clk_r <= spi_clk; How...
View Article