Dear All,
I am using a veriloga model symbol in my schematic.
But when I am running the simulation I am getting the following error:-
ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos_sch cmos.sch schematic veriloga verilogams ahdl" for instance I0 in cell IDEAL_COMP_test.
Either add one of these views to: Library: VERILOG_A_MODEL Cell: IDEAL_COMP or modify the view list to contain an existing view.
Could anybody please tell why this is happening ?
Kind Regards,