Import Synthesized Verilog Netlist to Virtuoso

I am trying to import a synthesized verilog netlist to virtuoso (IC615). The problem I have is, the standard cells are missing. I do not know what library file I should add to the library manager, as there is no libraray definition in the design kits/examples/cds.lib.

 The design kits I am using is IBM CMOS7RF. It seems that the synthesize library for Synopsys cannot be used in Cadence Virtuoso.

 Thank you for your help.