How to find correlation parameter between two layout devices?

I have done schematic and layout of its design in layout XL. I use cadence 6.1.5 and UMC 90nm technology library. For a mismatch analysis I will be doing monte carlo simulation.

I have to understand that ADE XL asssumes the correlation coefficient cc = 0. But typically a statement is added to netlist file to indicate cc = 0.75. Matching could be improved by employing careful design techniques. Assuming that one follows such techniques, then the cc has be close to 1. My question here is, how do we know the cc between two transistors from the layout tool. Please suggest me how to find the cc.

Thanks

Jagadish