Hi Andrew,
I pray you'll find this and find the time to respond.
I want to write netlist formatters to be used with spectre and amsdesigner (different formatters for different simulators, of course).
What I found in the documentation is, how to integrate a new simulator, which seems to be meant for non-Cadence products. In my case, it seems a overkill, since I do want to simulate with spectre, later maybe with amsdesigner.
The whole idea evolves around this problem: the electro-analogous systems, that I want to design, use signals which are single connections physically and bussed signals for simulation. For consistency, I want just one set of schematics and create appropriate netlists for simulation and physical verification from them. Preferrably, the schematics would represent connections as single ports. Thus my idea to customize netlisting for spectre.
Could you please comment on where to best place the resolution of single vs bus for my purpose, and point me someplace how to start the netlist customization?
I also have looked at the netlist procedure property, that can be attached to a cell. This enables me, to manipulate how instances of this particular cell are printed into the netlist of a schematic. However, it leaves me with the problem, how to also manipulate the interface of this schematic netlist, i.e. the subckt/module definition. Is there a similarily simple way to modify these as well?
Thank you in advace for any hint and help.
Kind Regards,
Jörg