How can I identify the proper standard library for HDL (VHDL, VHDL-AMS, Verilog, VerilogA) and include it in Virtuoso 6.1.4 so that I can create Cell Views of type VHDL, VHDL-AMS, Verilog or VerilogA.
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How can I identify the proper standard library for HDL (VHDL, VHDL-AMS, Verilog, VerilogA) and include it in Virtuoso 6.1.4 so that I can create Cell Views of type VHDL, VHDL-AMS, Verilog or VerilogA.