Help on CONFORMAL LEC flow using Synopsys's Design Compiler netlist

I'm trying to setup flow for using CONFORMAL LEC with DC netlist, and facing few problems in mapping.

--> Conformal doesn't map the RTL(async neg reset) with its counterpart  in netlist(DC). 

---> Conformal Doesn't map the "SNPS_CLOCK_GATE_HIGH" latch 

 **************my dofile is as follows (till it goes into lec mode)

     reset

    set log file <  >

     "sourcing project specific variables"

    set undefined cell black_box

      add notranslate filepathnames <  >

      add search path

      read library -verilog2k  

       read design -noelaborate -verilog2k -nosensitive  -golden <>

         read design -noelab -systemverilog -nosensitive -golden <>

      elaborate design -golden <>

      read design  -verilog 2k -revised <>

        set flatten model -nomap -latch_transparent -latch_merge_port -seq_constant -gated_clock -seq_redundant -nodff_to_dlat_zero -verbose

 set system mode lec

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please provide me the basic flow for CONFORMAL--DC netlist

regards,

rafeeq