Topology extraction - probe. Simulation fails vias due to via model errors.
Tried the board simulation in 16.3, 16.5, 16.6 errors in all attempts. Rexacted the via models from the board file, failure.
Moved to a different box to run the simulations, there were no errors.
Differences between systems - Windows 7 vs. Windows XP. Simulations run on windows XP box.
Question: Is there a known issue or work arround for PCB SI with windows 7?
Note: Latest hotfix (10/23/2013) on all versions.
I built the schematic, exported the netlist, and designed my PCB, but I did not see any connection btw the pcb and schematic.
Do I have to measure S-par in orcad capture or in allegre PCB? and how?
I am using Cadence 16.5
Many thanks.
Is there away to open a dynamic shape?
I tried axlDBOpenShape(current_shape) and Get "W- *WARNING* (axlDBOpenShape): Cannot edit a generated shape."
I use this to open static shapes and it works fine, but need to be able to open both.
Thanks,
Jerry
Hi,
I am using a kit which allows connecting PMOS body to ground. But once I am trying to connect them by globalNetConnect it generates short circuit error. Is there a way I can do that.
Thanks
Hi!
I am facing a very interesting issue that I have not seen/experienced before in cadence. I have a delay line and I am interested in finding the delay through it. When I use a vpulse to generate the input signal I get the expected output clock after the expected delay with no unusual effects. But when I generate the input clock using a verilog A block the output is delayed by the correct amount but the duty cycle of the output clock is consideably greater than the input clock.
The rise/fall times, frequency and pulse widths in both cases is exactly the same and the experimental setup is exactly the same. I am running the simulation in conservative preset mode.
Any idea what could be causing the issue and which results to trust.
Thanks and Regards,
MTP
I'm seeing some very strange behavior clicking certain menu items in Allegro
after opening a form with blocking on. I'm wondering if the is a way around this.
I create the form using: ConnectivityForm = axlFormCreate( (gensym) formFile nil 'connectivity_form_Action nil)
But if I select the "Info" button twice, or the Display->Highlight button twice, it just seems to go beserk.
The "Current Active Command" and the "Application status" on the very bottom left of the window just keep
flashing "Idle" and "Ready" while continuosly changing the Application status from red to green.
Has anyone seen this before? Anything I can adjust? Want any possible selection functions blocked.
Thanks, All help greatly appreciated. I can't have a user encountering this sort of behavior.
-Mike
Hi all,
I want to cancel a axlSingleSelectPoint() command if the user decided not to finish. I there a way to cancel axlSingleSelectPoint()?
Thanks,
Jerry
There is a segment of code below:
for(int i=0;i<10;i++)begin
$display("current random value: %0d", $random);
end
I use Cadence irun to compile and simulate this code. Although I add option " -seed random" to irun, but each time the result is same. It seems that $random is not controlled by -seed.
If I change $random to $urandom, it works! Each time I run, the result is not different.
So, my question is that, why $random is not controlled by -seed ???
Thanks.
Hi everyone,
Recently i did one small single layer board.i got some manufacuturing request to make the drill point as star or some other symbol.(while importing drill file black dots appearing.for manufacturer not able to find the center of block dots.some annual ring misalignment will happen)
Note:(i imported in CAM350 i could not find any option.is it possible to change like that )
Hello,
I would like to know if there is anyway to keep the same zoom and axis properties throughout multiple simulation runs. I see that there is a "Save as Default" button under the the plot settings but when I launch a new simulation the plot window resets to its original view ignoring whatever effect that button might have.
It's very difficult to compare plots if I have to set the view the way I need it each time.
Thank you.
I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors:
*ERROR* cell 'ind' is not defined.
*ERROR* cell 'pcdcap' is not defined.
*ERROR* cell 'bondpad' is not defined.
I have no idea what could go wrong? Same layout was LVS'ed nicely before with inductors and with above mentioned devices.
Any ideas what exactly could break suddenly?
How can the contents of the rdb be loaded?
I had a ADEXL simulation crash and want to look at the scalar calculated results.
I couldn't open the rdb file with the ADE results browser.
Hello and thank you for any help in advance,
I am having an issue with my Cadence environment/setup that will not allow me to see any of the parameter options for resistors (I have tried k1res, and multiple op resistors). Object properties only shows Library Name, Cell Name, View Name. No parameter options are available.
The CIW shows the following:
schHiObjectProperty()
*Error* putprop: first arg must be either symbol, list, defstruct or user type - nil
<<< Stack Trace >>>
(... in bicmos7wlresOParea ...)
(... in bicmos7wlresLength ...)
(... in bicmos7wlresGeom ...)
(... in bicmos7wlResCB ...)
(... in bicmos7wlsetDefaultsCB ...)
(... in cmrf7sfsetDefaultsCB ...)
(... in cdfAppendParamFields ...)
(... in unknown ...)
funobj@0x20280e80()
(... in schiLoadParamFields ...)
(... in schPostInsertRegions ...)
(... in schShowCB ...)
(... in schUpdateShowField ...)
(... in schInsertDefaultRegions ...)
(... in schObjectChangeCB ...)
(... in schObjEventCB ...)
(... in geEcEventCB ...)
apply('geEcEventCB '("schHiObjectProperty" "setup" ptrnum@0x1fd37860 2))
(... in geEcStartCmd ...)
(... in schHiObjectProperty ...)
schHiObjectProperty()
*WARNING* (SCH-1156): CDF parameter function has problem.
Can anyone diagnose my issue? I am running Cadence 6.1.6 and am in IBM 7RF.
Thank you,
Jake
Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.
For example, i have 2 signals sig1 and sig2. In verilog code:
assign #10 sig2=sig1;
Can I to synthesis some delay between 2 signals by rtl compiler commands such 'path_delay' or others?
Dear All,
I am using Allegro 16.2. I want to import a .DXF file ( attached in this post).
Basically it is a package symbol layout with mechanical holes.
I am confused in setting the layer mapping.
Could anybody please go through this file and tell me what to be done to import this file so that no informations in it is missed.
Kind Regards,
All,
While building a series of slots, I have been coming across a pink bar in my slot. I turned on all my layers but am unable to see it on the .brd. Bar is not present in symbol. It seems to have no effect on thw board, so , what is it?
-Ron Scott
Hi Andrew,
when simulating a circuit in cadence ic610 i get the below error -
Loading /home/daglitch/cadence/installs/MMSIM61/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ...
cpp: error: unrecognized option '-$
spectre completes with 1 error, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.
is this error due to installation issues? i am not able to figure out. please help.
thanks
using IC 5.10.40 in cadence ,,
i want to do corner analysis , i studied some manuals related to this ,, but i didn't understood how to add the process corners to my simulation ,, in this window " Add process " it is not showing any files ,, please help me to proceede ..
here i am attacthing the image also ,, pls hlep
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