Hi,
In the context of fractional plls, the nonlinearity in the PFD+CP transfer characteristic would result in noise folding which would increase the low freq phase noise.
I want to create a simple setup to capture in spectre simulations using
1.) quantisation noise by using zvcvs ( just by plugging coefficents of NTF of sigma delta modulator(z domain TF))
2.) vcvs to create the nonlinear transfer char using pwl vector/data file (curve obtained from stand alone chargepump simulation charge Vs. delta phi (input phase difference))
If i cascade these two sources 1,2 can I really capture the folding effects(intermodulation )?
but what simualtion (ac/tran/pac ) is needed for this kind of situation?
Ofcourse modeling modulator/chargepump in timedomain or using matlab for the same is fullblown exercise to capture it completely.
Thanks,
Vamshi
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simualting for sigma delta noise folding due to charge pump nonlinearity
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Monte Carlo Problem with Swept PSS and PAC
I am following the example in SpectreRF manual to simulate IP3 using swept PSS and PAC combination. I added output-referred IP3 as an output, using the Direct Plot form. When I run a nominal simulation using ADE L or XL, the IP3 output expression evaluates without any problem. But when I run a Monte Carlo analysis in ADE XL, the IP3 expression doesn't evaluate, and gives an error:
"Results pac are not available for ....../psf/mc1_separate/002. Use results() for a list of available results."
I also have other expressions using pss results. These evaluate correctly when I run the Monte Carlo without a pac analysis. But, when I include the pac analysis, 'some' of the pss-based expressions also fail to evaluate.
I searched on the Cadence support website etc, but couldn't find a solution that works.
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Modify netlist of a block and resimulate (CDL.... CDF....)
Hello everyone,
I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a spectre view before by following this tutorial:
But it was just a single resistors, and the library binding as I understand was by default analogLib, so it was relatively simple.
This time, I want to modify a netlist with mosfets from TSMC and capacitors from analogLib (C extraction of a switch architecture I'm trying out). I got the netlist exported from CIW---> File ---> Export ---> CDL ---> choose the library/cell/view name and left all other options at default. Here is the output: http://www.pastebin.ca/2519207
When I try to simulate this block using the technique in the tutorial I linked above, (CIW ---> CDF ---> Edit ---> ...) I get the following error:
================================
Notice from spectre in `sw3_and_constantvgs_1_editable', during circuit
read-in.
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
159: Use subckt `PD' as the master of `MI8|M0'
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
160: Use subckt `PD' as the master of `MM28'
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
161: Use subckt `PD' as the master of `MM27'
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
162: Use subckt `PD' as the master of `MI7|M0'
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
163: Use subckt `PD' as the master of `MM25'
Further occurrences of this notice will be suppressed (except in log
file).
Error found by spectre in `sw3_and_constantvgs_1_editable', during circuit
read-in.
ERROR (SFE-400):
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
159: The instance `MI8|M0' does not have a valid master.
ERROR (SFE-400):
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
160: The instance `MM28' does not have a valid master.
ERROR (SFE-400):
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
161: The instance `MM27' does not have a valid master.
ERROR (SFE-400):
"/home/caglarozdag/projects/TMSCOZDAG/cadence/sw3/sw3_and_constantvgs_1_editable"
162: The instance `MI7|M0' does not have a valid master.
...
etc.
================================
As far as I understand, capacitors in my netlists are taken from analogLib by default, so no problem there, just as it worked with my single resistor attempt. But the simulator is confused about how to handle the pchannel and nchannel mosfets.
If my understanding of the problem is correct, my question is: How can I bind these mosfets to the tsmc mosfet models? Do I have to do this during my netlist export? Do I have to do this during my CDF edit?
Thank you very much,
-Caglar
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Algorithm used for implementation of Division
Hi
What is the default algorithm used for hardware implementation of division operation when synthesised using RC Compiler. Like the code below
begin
quot[n:0] = divd/dvsr;
remi = divd%dvsr;
end
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Hierarchy Editor - Setting schematic view recursively within a tree
I'll try and explain my problem clearly first (sometimes there is an alternative solution).
I have a chip with distinct sections. Schematically they reside in different instances (eg I0 and I1).
I want to simulate everything within the section I0 using behavioural models and I1 with primitive models.
Within the view list I put my behavioural model before the schematic model name and that takes care of chosing the behavioural model.
For example my view list is: spectre schematic_behav cmos_sch schematic veriloga ahdl
Unfortunately this forces the I1 to also use behavioural models. While I *could* individually choose the models for the instance this is painful as there is a very large hierarchy into which I would have to decend and many individual instances (eg I1.level1.level2... ...level20).
Is there an easy way that I can define that everything in the hierarchy I0... uses schematic_behav and everything in the hierarchy I1... uses schematic?
Thanks
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ocean XL
Hai,
I am very much new to oceanXL script.
By using "save M1.m1:oppoint", i can't plot small signal parameters of MOS in ocean script.
The expression willl appear as
ocnxlOutputExpr( "getData("M1.m1:gm" ?result "dc-dc")" ?name "namegm" ?plot t ?save t).
I would be thankful if anybody can post the solution for the above problem.
Thanks,
krishna
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Is it possible to have different run modes for different tests in the same ade xl view?
Let's say we have two tests in an ade xl view. I want to choose Single Run, Sweeps and Corners for the first test and for the second test I want to run Monte Carlo Sampling. I tried but I couldn't have separate Output Setup for every test and the Output Setup is common for all the tests. So I am not able to specify different run modes for different tests in the same ade xl view.
Thanks
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Pin/terminal locations on symbol
Am I following the correct path?
geGetSelSet()~>instTerms~>term~>??
What is the path the find the pin/terminal location of a symbol in a schematic?
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[Need Help]Cadence16.6 Entry point not found, could not be located in the dynamic link library ordb_dll.dll
Install cadence 16.6 ok, but fails to open the exe.
Capture fails is just as the picture.
Allegro also fails, says could not be located in the dynamic link library cdscommon.dll. See the pic.
I used to install cadence16.3 and pads9.3, but before the installation of 16.6, I uninstall these two softwares.
After the failure, I reinstalled 16.6 for 2 times, all the same symptom.
I moved the CDSROOT information to the front of "PATH" in the environment variables, no effect. My computer is XP SP3.
I work at Freescale, we use the company dynamic license.
Thanks!
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skill writing style
I am new to skill and was looking at skill codes available on the web. I found abMapAndWire.ils by Andrew Beckett and noticed that variables are assigned in the first form below rather than the second. What are the differences? and advantages of the former? Tried searching the web and this forum and couldn't find something that directly mentioned these, probably because I don't know the proper names for them.
Form 1 (syntax form???):
(setq pin (car (getq terminal pins)))
Form 2 (assignment???):
pin=car(terminal~>pins)
Also, in the skill language reference, the syntax is given as
setq( x 5 )
rather than
(setq x 5)
What are the differences? and the preferred way?
Thanks
Regards
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How to disable vr_axi checks
Hi I am new to vr_axi enviorment,in my testbench i have some axi interfaces. I want to understand how to disable vr_axi checks like below
"ERR_VR_AXI190***"
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Force a callback when a form is canceled?
I've got a close button on my form, but is there a way to force a similar callback to be invoked
when the upper right "X" button is clicked? I'd like to make sure that I do some highlight cleanups
when my form gets closed reguardless of how the user dismisses the form.
Thanks, -Mike
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bbox values in menu
Is there a way to store several bbox values in a menu without converting it to a string?
Example of value
bboxList = '(((131.8625 -760.5125) (131.8875 -760.4875)) ((131.8625 -749.5125) (131.8875 -749.4875)))
I have tried several of the hiCreate* menus but it seems the functions are wanting strings or a single coordinate list.
Paul
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[Help] PADS layout to Allegro PCB translation
Hi all,
First, thanks for the time of you on this post.
I have a 8-layer PADS PCB layout designed by other people, which you can see from the attached Figure 1. What I want to do now is to extract the footprints of components in the PADS board layout to Allegro, so I don't need to redraw the footprint of some component. I have done some homework on the procedure, which is explained below, but still can't get it done.
The version of the PADS software is 9.5. The Allegro version is 16.6.
1: First, export the PADS PCB layout into .sci format. The settings is in attached Figure 2. Is it correct?
2: Copy the default pads_in.ini file to my directory. The contents of this file is listed in Figure 3. But I don't know how to modify it based on my case.
3: Launch in Allegro that File-->Import-->CAD Translator-->PADS, choose the .asc and .ini file, and run Translate.
I get some errors here, which is listed below:
Using translator version @(#)$CDS: pads_in.exe v16-6-112X 3/11/2013 Copyr 2013 CADENCE DESIGN SYSTEMS.
Reading PADS ASCII file header.
PARSE ERROR: Unrecognized format in header line of input file.
Line 1: !PADS-POWERPCB-V9.5-BASIC! DESIGN DATABASE ASCII FILE 1.0
ERROR: Finished with errors.
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Warnings during the use of Spectre
Hi~ I am kinda a newbie to Cadence. Don't laugh at me if my questions are stupid :)
I am using version 5.1.0, and IBM design kits.
Some warnings come up when I start up cadence.
1. Startup:
*WARNING* No user triggers registered for viewType schematic.
*WARNING* No user triggers registered for viewType schematicSymbol.
*WARNING* No user triggers registered for viewType maskLayout.
What do those mean? How to get rid of this?
2. When I open the schematic, click any simulation tool, either Analog environment,or ADS dynamic link . It shows:
*WARNING* ERROR (LM -30): license server ("") does not support feature "34510" (run 'lic_error -30' for more information)
*WARNING* ERROR (LM -30):
license server ("") does not support feature"Analog_Design_Environment_L" (run 'lic_error -30' for more information)
I check my licenses from "Options", I can only "check out" ("95210 Virtuoso(R) Analog Design Environment XL"), but not ( "34510 Virtuoso(R) Analog Design Environment" .
So is this a serious problem? I can still run simulations.
3.While doing simulation, the following show up:
spectre (ver. 5.10.41.071008 -- 10 Jul 2008).
Opening directory
/tmp2/IBM130/IBM_PDK/cmrf8sf/V1.5.0.1DM/Spectre/models/coupled_cpw.va.ahdlcmi/
(770)
Compiling ahdlcmi module library.
Failed to compile ahdlcmi module library, see
/tmp2/IBM130/IBM_PDK/cmrf8sf/V1.5.0.1DM/Spectre/models/coupled_cpw.va.ahdlcmi/
for details
Could not open ahdlcmi module library
/tmp2/IBM130/IBM_PDK/cmrf8sf/V1.5.0.1DM/Spectre/models/coupled_cpw.va.ahdlcmi/obj/Linux2.6.18-128.1.1.el5+gcc/optimize/libahdlcmi.so
/tmp2/IBM130/IBM_PDK/cmrf8sf/V1.5.0.1DM/Spectre/models/coupled_cpw.va.ahdlcmi/obj/Linux2.6.18-128.1.1.el5+gcc/optimize/libahdlcmi.so:
cannot open shared object file: No such file or directory
Opening directory
/tmp2/IBM130/IBM_PDK/cmrf8sf/V1.5.0.1DM/Spectre/models/mvcapdg.va.ahdlcmi/
(770)
Compiling ahdlcmi module library.
Failed to compile ahdlcmi module library, see input.ahdlcmi/ for details
Could not open ahdlcmi module library
input.ahdlcmi/obj/Linux2.6.18-128.1.1.el5+gcc/optimize/libahdlcmi.so
input.ahdlcmi/obj/Linux2.6.18-128.1.1.el5+gcc/optimize/libahdlcmi.so:
cannot open shared object file: No such file or directory
So, is it because of my version of spectre doesn't support AHDL? How to fix this?
Thanks!!!
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Skill Script for off-grid correction of donut shape?
Hi,
I have been looking for a Skill script which corrects off-grid edges of a donut shape in Cadence(IC6) Layout editor. I have found this script but it says it is not for donut. http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=1800103.
What I need to do is that I need to draw a donut for real tape but it is off-grid so I need a script for grid correction. Actually, I don't know which way is better: drawing donut in layout and putting edge of it on grid with a script or drawing on-grid donut with Skill script from the beginning. I prefer the first one since in addition to donut I may have other off-grid shapes which need to be corrected.
I will appreciate if you can provide the Skill script for this purpose.
Thanks,
yayla
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Adding Layout block from Encounter to custom design
I managed to get Encounter auto-route and place the design, imported it into the Virtuoso environment as a Layout view, then runned DRC, then runned LVS versus the CDL file of standard cells and verilog file exported from encounter.
Now, I want to put this layout inside another custom layed out design. Right now, I have one design with some transistors, manually connected in schematic, and manually layed out, so I want to add this layout to that design and put it in a top level block, and then DRC and LVS it.
The way I do manual designs is, I first do schematics by hand in SchematicsXL, then I export the CDL netlist, then I pass it through the LVS script of IBM kit to convert it to LVS suitable format. Then I do layout, and do LVS versus the CDL netlist.
But in this case, I am going to use the layed out and separately LVS'ed Layout I have in another cell. That another cell has only Layout view, and a Symbol view I created for it.
The thing is, once I put that symbol inside a schematic with custom elements, and try to export netlist, the system complains saying that there is no "schematic" view.
In my export window of netlist as a View List there is: auCdl schematic, and as stop view: auCdl.
My question is: How do I integrate my imported Layout block on a schematics level in my top level block with manually designed stuff around it? Because, there is no "schematic" view in that Layout block, I did its LVS versus the CDL file of standard cells lib and verilog file from encounter.
I searched and know that people also do something like, import verilog to schematics. But then, my another question is, can I avoid that step? I really do not want to deal with schematics, even though this design is not that big, but I dont want to deal with it during the next very big designs.
Is there a way to export netlist from schematics with symbol of another imported block which only has Layout view without dealing with its schematics?
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Trigger Warning at Virtuoso start up
*WARNING* (DEBASE-102068): No user triggers registered for viewType schematicSymbol.
*WARNING* (DEBASE-102068): No user triggers registered for viewType maskLayout.
*WARNING* (DEBASE-102068): No user triggers registered for viewType maskLayoutXL.
*WARNING* No application registered for prefix awv.
*WARNING* No application registered for prefix awv.
*WARNING* No application registered for prefix awv.
What are these warnings and how do I get rid of them? What do these mean? My IC version is IC6.1.5-64b.500.15
Thank you in advance.
*WARNING* (DEBASE-102068): No user triggers registered for viewType maskLayout.
*WARNING* (DEBASE-102068): No user triggers registered for viewType maskLayoutXL.
*WARNING* No application registered for prefix awv.
*WARNING* No application registered for prefix awv.
*WARNING* No application registered for prefix awv.
What are these warnings and how do I get rid of them? What do these mean? My IC version is IC6.1.5-64b.500.15
Thank you in advance.
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Warning (TECH-230035): warning when create library
Hi everyone,
I would like to ask about a warning in CIW. My systems: Cadence IC615, IBM cmrf7sf V2000 pdk. When I try to create a library which "Attach to an existting techfile" option, the CIW displays warning:
*WARNING* (TECH-230035): User-defined rule "minExtensionDistance" in constraint
group "foundry" of techDB "cmrf7sf" conflicts with
a built-in constraint with the same name.
You may write out "constraintGroups" section to an
ASCII file, reopen the technology database in "a"
mode, and reload the file to update the database.
Another option is to rename this rule. I searched on Google and found only one link:
http://www.cadence.com/Community/CSSharedFiles/forums/storage/38/1310402/qrc.inverter_test.log.txt
I read. However, I could not understand what I should do. Can anyone figure out this problem, please?
Thank you so much.
Regards.
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Simulation Profile Setup Issues
Hey I'm pretty new to PSPICE and I've followed every tutorial there is and they all pretty much say you can choose the "none" option to avoid the inherit from issue when there are no .sim files to inherit from. I have Orcad_lite_9_2 and I'm in the"PSPICE AD Lite Edition" and I went to New Simulation Profile and I see the fields for "Profile name" and "Inherit from existing profile" as well as the "Create" "cancel" "help" and even "..."(browse) buttons but I don't see a "none" option anywhere. I've searched for hours and I've got a project I have to get finished.
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