I was wondering if it is possible in my ADEXL prerun script to get the run mode of the ADEXL session that started the script. Basically, I would like to update design varibles if the current run is a Monte Carlo run (based on another Monte Carlo sim). However, if it is a Single Run, Sweeps and Corners, then I would like to do nothing with the variables. Any ideas how to do this?
Thanks
Hi all,
I was recently working on a mixed-singal simulation with AMS. To speed up the simulation, in ADE, I chose simulation performance mode as "APS", and manually chose 8 threads. In ADE, everything goes well, 8 cpu cores were brought up for the simulation, the simulation finished quite soon.
Then I generated an ocean script from ADE, and tried to run the script in OCEAN enviorment. But this time, it seems only one cpu cores was working and thus a very long simulation time was experienced. I checked there are the following warnings:
I use Cadence ic6.1.5-64b.500.16.2; MMSIM 121
the machine I used has 8 cores.
The automatic generated ocean script was as following (simplified) :
---------------------------------------------------------------------------------------------------
simulator( 'ams )
solver( 'Spectre )
design(....)
ocnAmsSetOSSNetlister()
resultsDir( "..." )
connectRules()
globalSignal(?name "gnd!" ?lang "CDBA" ?wireType "wire" ?discipline "" ?ground "YES")
globalSignal(?name "vdd!" ?lang "CDBA" ?wireType "wire" ?discipline "" ?ground "NO")
modelFile( )
analysis('tran ?stop "30n" )
desVar( "vdd" 1.5)
envOption(
'netlisterMode "OSS-based"
'invocationStyle "irun"
'builtinuser nil
'cleanSnapShot list(t)
)
option( ?categ 'amsTurboOpts
'numThreads "8"
'mtOption "Manual"
'uniMode "Turbo"
)
temp( 27 )
run()
Thanks in advance for your help!
Hi,
I would like to do corner sims with ocnXL, save only the output of each run in a data file and nothing else. Basically I would like to delete all the the rest of sim data . In ocn ADE I could do it by each time selcting a model file and doing "run" in a loop. How could I possibly do it in OcnXL. Thanks much.
Shaf
Below is the veriloga code i wanted to run in spectre to record zero crossing times.
I am getting the error:
Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "last=$last_crossing<<--? (V(in), +1); "
"/home/srm/cadencesch/varcap/last_cros/veriloga/veriloga.va", line 17:
syntax error.
// VerilogA for varcap, last_cros, veriloga
`include "constants.vams"
`include "disciplines.vams"
module last_cros(in);
input in;
voltage in;
parameter integer dir=1 from [-1:1] exclude 0;
integer fp;
real last;
analog begin
last = 1.0;
@(initial_step)
fp= $fopen("zerocrossings");
last=$last_crossing (V(in), dir); <--------------------------------------line number 17
@(cross(V(in), dir))
$fstrobe( fp, "%0.10e", last);
@(final_step)
$fclose(fp);
end
endmodule
I need some help if possible on the following issue:
*WARNING* (reader): string at line 1 was not terminated on EOF, '"' added at line 2 of string "...)"
I made a lot of search on google unfortunately without success.
Thank you in advance.
Note: The complete Log is given below.
############################################################
Program: @(#)$CDS: virtuoso version 6.1.5 09/07/2011 12:14 (sfsol608)
$
Sub version: sub-version IC6.1.5.500.6 (32-bit
addresses)
Loading geView.cxt
Loading menuBuilder.cxt
Loading
schView.cxt
Loading selectSv.cxt
Loading pvsskill.cxt.
Loading
LVS.cxt
Loading layerProc.cxt
Loading xlUI.cxt
*WARNING* (reader):
string at line 1 was not terminated on EOF, '"' added
at
line 2 of string "...)"
*WARNING* (reader): a '(' at line 1 was still
unclosed on EOF, ')' added
at line 2 of string "...)""
*WARNING* (reader): illegal character '$' ignored at line 1 of string "... $"
*WARNING* (reader): illegal character '$'
ignored at line 1 of string "... $"
*WARNING*
(reader): illegal character '$' ignored at line 1 of string "... $"
*WARNING* (reader): illegal character '$'
ignored at line 1 of string "... $"
*WARNING*
(reader): illegal character '$' ignored at line 1 of string "... $"
*WARNING* (reader): string at line 1 was not
terminated on EOF, '"' added
at line 2 of string "...)"
Loading auCore.cxt
Loading vhdl.cxt
Loading seismic.cxt
Loading ci.cxt
Loading ams.cxt
Virtuoso Framework License (111) was
checked out successfully. Total checkout time was 0.11s.
Loading NCSU CDK
1.5.1 customizations...
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
adle
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
asimenv
*WARNING* envSetVal: Can't set the value of variable 'width',
in tool[.partition] 'asimenv.plotting' - it has not been
registered.
*WARNING* envSetVal: Can't set the value of variable 'height',
in tool[.partition] 'asimenv.plotting' - it has not been
registered.
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
ddserv
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
layout
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
schematic
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
ui
loading vars from
/home/dbenamrouche/uscn/ncsu-cdk-1.6.0.beta/cdssetup/cdsenv for tool
layoutOptimize
loading vars from ~/.cdsenv for tool layoutOptimize
loading
vars from ~/.cdsenv for tool asimenv
Loading NCSU SKILL routines...
Done
loading NCSU_CDK customizations.
############################################################
Anybody have a SKILL script that will make a small circle with crosshairs, at the symbol origin on PACKAGE GEOMETRY/BODY_CENTER, that will run from inside the symbol editor?
I managed to get Encounter auto-route and place the design, imported it into the Virtuoso environment as a Layout view, then runned DRC, then runned LVS versus the CDL file of standard cells and verilog file exported from encounter.
Now, I want to put this layout inside another custom layed out design. Right now, I have one design with some transistors, manually connected in schematic, and manually layed out, so I want to add this layout to that design and put it in a top level block, and then DRC and LVS it.
The way I do manual designs is, I first do schematics by hand in SchematicsXL, then I export the CDL netlist, then I pass it through the LVS script of IBM kit to convert it to LVS suitable format. Then I do layout, and do LVS versus the CDL netlist.
But in this case, I am going to use the layed out and separately LVS'ed Layout I have in another cell. That another cell has only Layout view, and a Symbol view I created for it.
The thing is, once I put that symbol inside a schematic with custom elements, and try to export netlist, the system complains saying that there is no "schematic" view.
In my export window of netlist as a View List there is: auCdl schematic, and as stop view: auCdl.
My question is: How do I integrate my imported Layout block on a schematics level in my top level block with manually designed stuff around it? Because, there is no "schematic" view in that Layout block, I did its LVS versus the CDL file of standard cells lib and verilog file from encounter.
I searched and know that people also do something like, import verilog to schematics. But then, my another question is, can I avoid that step? I really do not want to deal with schematics, even though this design is not that big, but I dont want to deal with it during the next very big designs.
Is there a way to export netlist from schematics with symbol of another imported block which only has Layout view without dealing with its schematics?
Hai! I found a code which will change cells from one lib/view to another.. in cadence sourcelink ...
I am using cadence IC6X version.. and a IBM(90nm) PDK kit ..
The code is working fine when I tried to convert cells from 'analogLib' to 'gpdk090'..
But when I tried this code in changing cells from 'analogLib' to 'IBM' models it's not happening..
I thought this is because of the following reason.. the IBM PDK kit defines the following params for w(width), l(length), m(multiplier) as
wf(string type),(wff float type), lf(string type), (lfffloat type) and mpl(int type)...
The params w, l, and m assigned as user defined params after running the code..
I tried to assign the w, l, and m values to the wf, lf and mpl ... the form displaying the values correctly(in schematic).. but when I attempt generate from source it is picking the transistors of default values but the form values remains unchanged.. (in the layout)..
I hope the problem is understandable.... If not I will provide some more information...
Can please some one guide me to achieve this............
Prabhakar. K -- Layout Engineer
Hi,
I had started to learn the Sig Explorer on cadence. I had an idea on the losses and other terminology used in the signal analysis. I had simulated an basic RLC network with the IO pulse as Input and IO tristate as Output side and intermediately the Dummy Probe had kept and the losses calculated.
But When i want to simulate the RLC network with far network and near network, i had inserted the micro strip in between the two networks. An sample tuto had explained some of the things with micro strip, but my question is in case of any micro strip is inserted the losses at the output side will be more or less?
Then micro strip parameters are represented as Impedance and PropDelay, trace geometry , velocity.
What is the prop delay and Velocity?
I have been using OrCAD PCB Editor for a short time and haven't really had any major problem. One thing that is very annoying is that when I am moving parts or text on the layout the curser jumps up to the right top corner when I select a part or text. This also makes the board shift to the left a short distance. It seem that there should be a setting that either enables or disables the curser to jump up to the visibility tools or something.
Please help.
Dear all,
I have a AND-OR structure written in RTL in a module. After the synthesis I see that the same logic is implemented using different logic elements in different modules. In one module I see AND-OR is formed with 4 instances, in other module with 5 instances.
Is there a way to tell RC to use exactly the same AND-OR structure in different modules, that are using same piece of RTL code?
Thanks,
Aram
Hi,
I'm trying to import some expressions into ADE-XL test environment using OCEAN. I created a SKILL file (foo.il) with the following:
session1 = axlCreateSession("foo")
handle1 = axlSetMainSetupDB(session1 "./data.sdb")
print "About to import outputs..."
axlOutputsImportFromFile(session1 "./outputs.csv" ?operation "overwrite")
axlSaveSetup()
exit
Then I run ocean (6.1.6.500.2) using ocean < foo.il
Here's what I get:
ocean> "About to import outputs..."nil
ocean> *Error* asiGet: no applicable method for the class - list(symbol)
If I invoke ocean in the interactive mode and enter the above command, it works fine.
Any help will be appreciated!
Thanks,
hpan.
To whom it may concern,
There are some forums for Allegro and Allegro SKILL, but is there any forum for Concept HDL and Concept SKILL ? I am curious why Cadence didn't create a forum for all of the products? One forum for each of its major product.
Best regards,
Jun
To whom it may concern,
There are some forums for Allegro and Allegro SKILL, but is there any forum for Concept HDL and Concept SKILL? I wish that Cadence could set up forums for all its products, one for each.
Best regards,
Jun
Hi All,
I have some basic questions about the display of allegro, as you can see from the attached figure 1,2, and 3.
In figure 1, you cans see the three RED pads in the same net. The top and the bottom ones seem to have some stipple pattern on it, but the middle one doesn't.
In figure 2, the nets of 3.3V, GND, and some of my signal (BLK), are in grey color, which make it harder to differentiate their layer.
In figure 3, the routing of net BLK are in a color of grey and red, which looks strange.
What I am wondering is how to make these color uniform? I mean, all the pads, trace on the top layer are all in a single color, for example, red. I don't want the grey color, and neither the stipple one.
Btw, I didn't set any stipple pattern in Color/Visibility, and set the pads and routes in the top layer in RED. but the final PCB seems strange...
I would appreciate your help. Thanks~~
Below is the veriloga code i wanted to run in spectre to record zero crossing times.
I am getting the error:
Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "last=$last_crossing<<--? (V(in), +1); "
"/home/srm/cadencesch/varcap/last_cros/veriloga/veriloga.va", line 17:
syntax error.
// VerilogA for varcap, last_cros, veriloga
`include "constants.vams"
`include "disciplines.vams"
module last_cros(in);
input in;
voltage in;
parameter integer dir=1 from [-1:1] exclude 0;
integer fp;
real last;
analog begin
last = 1.0;
@(initial_step)
fp= $fopen("zerocrossings");
last=$last_crossing (V(in), dir); <--------------------------------------line number 17
@(cross(V(in), dir))
$fstrobe( fp, "%0.10e", last);
@(final_step)
$fclose(fp);
end
endmodule
I am trying to create a netlist from ADE-XL through skill command. My intention is to create the same netlist which ADE-XL creates when user clicks "Run" button in ADE-XL.
I tried following options. But all of them don't take "Global Variables" in to account.
createFinalNetlist
asiFinalNetlist
asiExecuteFlowChart(o_session 'asiComposeSimInput)
Is there any other way to achieve this?
Thanks,
Ram
Hello,
I failed to search the manual and the forum to find a way to copy and rotate a shape I created with any agle like 15, 30, 45 etc.
I noticed some posts said that rotate with any angle may raise lithography issues. But in MEMS application, it's very popular to use all kinds of "strange" shapes. As the line/space is over 1um, the litho problem can be neglected. Then, what can I do in skill code?
Thanks.
I simulated
* source TRIAL
X_M1 -1 0 MEMRISTOR PARAMS: RON=10K ROFF=100K RINIT=130K D=10N UV=10F
+ P=1
R_R1 -1 0 1k TC=0,0
V_V1 -1 0
+SIN 0V 0.1V 0.56Hz 0 0 0
with the the memristor code
.SUBCKT memristor Plus Minus PARAMS:
+ Ron=10K Roff=100K Rinit=130K D=10N uv=10F p=1
***********************************************
* DIFFERENTIAL EQUATION MODELING *
***********************************************
Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}
Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}
Raux x 0 1T
* RESISTIVE PORT OF THE MEMRISTOR *
*******************************
Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}
Roff aux minus {Roff}
***********************************************
*Flux computation*
***********************************************
Eflux flux 0 value={SDT(V(plus,minus))}
***********************************************
*Charge computation*
***********************************************
Echarge charge 0 value={SDT(I(Emem))}
***********************************************
* WINDOW FUNCTIONS
* FOR NONLINEAR DRIFT MODELING *
***********************************************
*window function, according to Joglekar
.func f(x,p)={1-(2*x-1)^(2*p)}
*proposed window function
;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}
.ENDS memristor
and I created a new simulation AC sweep profile .AC DEC 10 0 10000
and i get the error
ERROR-- INVALID VALUE
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
and I donot know what to do?
So please can anyone help me...
I am following the example in SpectreRF manual to simulate IP3 using swept PSS and PAC combination. I added output-referred IP3 as an output, using the Direct Plot form. When I run a nominal simulation using ADE L or XL, the IP3 output expression evaluates without any problem. But when I run a Monte Carlo analysis in ADE XL, the IP3 expression doesn't evaluate, and gives an error:
"Results pac are not available for ....../psf/mc1_separate/002. Use results() for a list of available results."
I also have other expressions using pss results. These evaluate correctly when I run the Monte Carlo without a pac analysis. But, when I include the pac analysis, 'some' of the pss-based expressions also fail to evaluate.
I searched on the Cadence support website etc, but couldn't find a solution that works.