Virtuoso 6.1.5 to encounter

September 25, 2013, 12:05 am

≪ Previous: extracted view simulation in OCEAN

Hi All,

I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.

=====================================================

--> <folderPath>/BackEnd/

* LEF P & R model (in <folderPath>/BackEnd/lef)
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.3.lef
- FOA0I_R33_T33_GENERIC_IO_ANT_V55.lef
- foa0i_r33_t33_generic_io.3.lef
- foa0i_r33_t33_generic_io.lef
- header3_V55.lef
* physical compiler database (in <folderPath>/BackEnd/phycompiler)
- foa0i_r33_t33_generic_io.3.pdb
- foa0i_r33_t33_generic_io.3.plib

--> <folderPath>/TECH/

* Cadence DFII environment files (in <folderPath>/TECH/dfii)
- FOA0I_R33_44.tf
- cellout.tab
- display.drf
- layer.DEFINE
- pg_sout3.tab
- pg_sout4.tab
- streamOut.map
- streamin.tab
- txtfont.tab

====================================================

Which is better out of the two options

1. Do IO placement in virtuoso itself

2. Take it to encounter - (How to do it ?)

Thanks,Shameel

↧

Virtuoso 6.1.5 to encounter

September 25, 2013, 12:05 am

≫ Next: IO placement

≪ Previous: Virtuoso 6.1.5 to encounter

Hi All,

I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.

=====================================================

====================================================

Which is better out of the two options

1. Do IO placement in virtuoso itself

2. Take it to encounter - (How to do it ?)

Thanks,Shameel

↧

IO placement

September 25, 2013, 12:07 am

≫ Next: Create application form trigger??

≪ Previous: Virtuoso 6.1.5 to encounter

Hi All,

I have implemented a digital block in transistor level using virtuoso 6.1.5 . I want to do the IO placement for it. The IO library that I had has the following files in it.

=====================================================

====================================================

Which is better out of the two options

1. Do IO placement in virtuoso itself

2. Take it to encounter - (How to do it ?)

Thanks,Shameel

↧

Create application form trigger??

September 20, 2013, 8:40 am

≫ Next: ocean XL monte carlo abort on internal error

≪ Previous: IO placement

Hello,

We want to create our custom button on on a certain predefined by some of our third party vendors Application form. It can easily be done with code like bellow:

hiAddField(certainForm list(our_custom_button 200:600 200:25 140))

But the problem is that the form should be opened in order button to be added. So it will be best if some trigger could be set whenever the form is opened our button looading procedure to be executed.

Do you know if such kind of triggers exist?

Thanks,

tyanata

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ocean XL monte carlo abort on internal error

September 20, 2013, 2:18 pm

≫ Next: Access elements of symbol in skill

≪ Previous: Create application form trigger??

Dear All,

In ocean XL monte carlo simulation, it seems the job controller will abort all unfinished jobs once it detects that one of the simulation has an fatal/internal error. Is there a way to resume the computation even if there is such an error?

Thanks,

Fred

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Access elements of symbol in skill

September 25, 2013, 3:28 pm

≫ Next: Schematic Probe highlight thickness

≪ Previous: ocean XL monte carlo abort on internal error

corModelSpec = (("/home/bin/toplevel.scs" "top_sf"))

corModelSpec is of a type symbol. How can I access only second string out from this, so that my output will be top_sf.

I tried rindex but it doesn't quite give the desired output.

param_value=rindex(strcat(corModelSpec) "t") ;

println(param_value)

Output: "top_sf\"))"

I would like to get rid of brackets and double quotes from the output. Any help would be appreciated. Thanks.

-Sandeep

↧

Schematic Probe highlight thickness

September 25, 2013, 4:18 pm

≫ Next: Hierarchical Parasitic Extraction & Cadence Tools

≪ Previous: Access elements of symbol in skill

I am trying to do something like CCR 1844262. I have a common SKILL file designers in my group load and I would like to implement changing the probe width there (if that is even the best way to do it).

Changing the default display.drf in the cadence install directory is not an option.

I could not find anything on how to change display settings using only SKILL and not a drf.

↧

Hierarchical Parasitic Extraction & Cadence Tools

October 2, 2010, 9:50 am

≫ Next: No Pspice template issue

≪ Previous: Schematic Probe highlight thickness

Hello Everyone,

I have come up with a question and i would really want to hear the opinion of more expert people in here about my issue concerning parasitic extraction in an hierarchical design.So,let me pose my question more clearly :

I have an hierarcical design.Let's say that the top level schematic's name is A.

A consists of two sub-cells that i will give them the name B1,B2.

B1 has 6 more sub-cells (C1,C2,C3,C4,C5,C6).

I know hot to perform hierarchical RCX with the Hierarchy Editor tool of Cadence but...if i want to take into account the parasitics of the interconnections of some specific sub-cells what is the way to implement the extraction procedure and take correct results?Can Hierarchy Editor do this or i need another tool of cadence and subsequently an extra license for this?

A testbench for me in the hierarchy editor would be :

A -->Schematic

B1 -->Schematic

C1,C2,C3,C4 -->Schematic

C5,C6 --> av_extracted

B2 -->av_extracted

and i want to extract as well the interconnections between C5-C6 cells and between B1-B2 cells.I should note that all sub-cells have their own physical implementation (layout view in other words).

Thanks in advance for any helpful answer.

My Best Regards,

Jimito13

↧

No Pspice template issue

September 24, 2013, 3:57 am

≫ Next: analysis

≪ Previous: Hierarchical Parasitic Extraction & Cadence Tools

Hi,

I've had a stable working testbench in Orcad Capture until several days ago when something happened and some of the components "lost" their template. But the issue appears to be not limited to my testbench. I tried building a simple circuit from scratch (just a voltage source, resistor and ground) using pspice_elem library for the resistor. And I get the same "No Pspice template for R1, ignoring" message. It seems to me as environment related issue. Any help will be appreciated. Thanks in advance.

↧

analysis

June 26, 2013, 8:54 pm

≫ Next: Need workaround for duplicate veriloga module name issue

≪ Previous: No Pspice template issue

hello

↧

Need workaround for duplicate veriloga module name issue

September 26, 2013, 4:00 am

≫ Next: how to simulate delay of a wire?

≪ Previous: analysis

Hi,

For some reason I'm including the same model file twice in a spectre simulation. In that .scs file I have a ahdl_include statement that includes a varilog-a model. Now because I'm loading this file twice, It is throwing an error saying that

"A built-in or regular master with name xyz already exists, cannot create an alias master with same name"

Is there a option similar to duplicate_subckt=warning for verilog-a model.

Thanks,

Jagadish

↧

how to simulate delay of a wire?

September 26, 2013, 3:03 am

≫ Next: verilogA encryption for spectre

≪ Previous: Need workaround for duplicate veriloga module name issue

Hi all,

We know it takes time for electrical signals to travel from one end of a wire to the other. The wavefrom seen at one end of a wire should be different from the waveform seen at the other end. How can I simulate them? At first, I though I could place two pins at the two ends. Apparently, it didn't work. Do you know any ways I can achieve that?

Thank you very much!

↧

verilogA encryption for spectre

September 26, 2013, 1:29 pm

≫ Next: About Pinuse

≪ Previous: how to simulate delay of a wire?

Hello,

I would like to encrypt a compact analog model written in verilogA and executed with spectre and ultrasim.

In the spectre doc, I found that a netlist could be encrypted wtih

spectre_encrypt [-i input_file] [-o output_file] [-all]

but what about a verilogA file?

Regards,

Fabrice

↧

About Pinuse

September 26, 2013, 5:57 pm

≫ Next: How to connect vias to specific layers

≪ Previous: verilogA encryption for spectre

Hi All, a newbie question. What exactly is pinuse in Allegro? and what implication does it place on the pins?

It seems like a description of the function of the pins which can be BI, POWER, GROUND ... etc. and they are assigned initially at the schematic capture stage.

Thanks in advance.

↧

How to connect vias to specific layers

September 26, 2013, 6:39 am

≫ Next: spectre commandline gives : -1.11111e+36 as a result. ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression

≪ Previous: About Pinuse

I have a design which has 7 layers. The top layer has only short stubs.

There are two layers for traces but they are sensitive signals and there is a solid ground plane above and below these two layers. I have connected these two planes at one point near the incoming supply. I also have a single ground plane as layer 7 which is noisy.

How do I connect a number of ground signals from Layer 1 to Layer 7 WITHOUT connecting to the other two ground planes, which would inject noise onto these planes?

When I try using the normal vias, they connect all planes from 1 to 7 and also 2 and 5, I just need layers 1 and 7 connected but they need to connect at the supply (one via connecting layers 1, 2, 5 and 7).

↧

spectre commandline gives : -1.11111e+36 as a result. ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression

September 19, 2013, 8:42 am

≫ Next: Does AMS envlp analysis ignore (* ignore_hidden_state *), etc... attributes?

≪ Previous: How to connect vias to specific layers

Hello,

I am encountering an issue when I launch some simulations with this commandline :

spectre simulations/design_test/montecarlo/$i/input.scs +log simulations/design_test/montecarlo/$i/mc_log_file.log

The $i value is the value for different path corresponding to different netlists to launch MC on.

In the result file I have the value : -1.11111e+36

Example : in my mcdata result file :

-1.11111e+36 -1.11111e+36 -1.11111e+36 -1.11111e+36 -1.11111e+36

Instead of something like :

0.23 0.87 1 0

I suspect a synchronisation issue between the result waveforms creation and the ocean export commands.

If I relaunch the command, it works well.

I think I have a solution, it's to launch a spectremdl command, but I wanted to highlight this weird behaviour, and i would like to know if i can change something slight to make it work better, jus with a spectre commandline?

In the log file :

Warning from spectre during Monte Carlo analysis `mc1'.

WARNING (SPECTRE-16002): Monte Carlo iteration 49 terminated prematurely because of the following error(s):

Error found by spectre during Monte Carlo analysis `mc1'.

ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression `expression_1=value(v("out_b_iv" ?result "tran") 4.775n)'.

ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression `expression_2=value(v("out_iv" ?result "tran") 4.775n)'.

ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression `expression_3=value(v("state_left" ?result "tran") 9.825n)'.

ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression `expression_4=value(v("state_right" ?result "tran") 9.825n)'.

Extract of the netlist :

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" checklimitdest=psf

mc1 montecarlo numruns=1 seed=12345 variations=mismatch sampling=standard donominal=no scalarfile="../monteCarlo/mcdata" savemismatchparams=yes mismatchparamfile="../monteCarlo/mismatchparam" mismatchscalarfile="../monteCarlo/mismatchdata" dumpdependency=mismatch dependencymapfile="../monteCarlo/mismatchdependency" dut=[ I0 I1 M2 M0 M1 ] savefamilyplots=no savedatainseparatedir=yes firstrun=50 {

tran tran stop=34.40nn write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile

element info what=inst where=rawfile

outputParameter info what=output where=rawfile

designParamVals info what=parameters where=rawfile

primitives info what=primitives where=rawfile

subckts info what=subckts where=rawfile

export expression_1=oceanEval("value(v(\"out_b_iv\" ?result \"tran\") 4.775n)")

export expression_2=oceanEval("value(v(\"out_iv\" ?result \"tran\") 4.775n)")

…

}

mcOptions options genmcdep=yes

save out_b_iv out_iv out_b out state_left state_right

saveOptions options save=selected subcktprobelvl=2

Thanks a lot !!

↧

Does AMS envlp analysis ignore (* ignore_hidden_state *), etc... attributes?

September 27, 2013, 2:47 am

≫ Next: noisefile in a vdc source modeled by Verilog-A

≪ Previous: spectre commandline gives : -1.11111e+36 as a result. ERROR (SPECTRE-8003): mc1_subckts: Error evaluating ocean expression

Dear all,

An error occurs regarding hidden states when running an AMS envlp simulation:

"ERROR (SPCRTRF-15177): ENVLP analysis doesn't support behavioral module
components with hidden states found in component
'worklib__DataPath__vams__0x10000001_behavioral'. Skipped."

A similar error is raised when using the built-in connect rule E2L_inhconn for example.

I have experimented with the VerilogA attributes (* ignore_hidden_state *), (* ignore_state *) and (* instrument_module *), however they seem to not make any difference, i.e. the same error is raised.

Can somebody confirm that these attributes are ignored in AMS envlp? Is there a workaround besides rewriting the Verilog-AMS code?

spectre version 11.1.0 32bit 08/14/2012 20:55 (usimamd64-23)

irun version 12.10-s005

Best regards

↧

noisefile in a vdc source modeled by Verilog-A

April 12, 2013, 5:30 am

≫ Next: Global relief settings

≪ Previous: Does AMS envlp analysis ignore (* ignore_hidden_state *), etc... attributes?

Hello,

Is it possible to read a noise file from Verilog-A?

I would like to add a known noise shape to a model of a vdc voltage source modeled by Verilog-A.

(I need to read data from a file and pass them to noise_table)

thank you very much

Best regards

Aldo

↧

Global relief settings

September 25, 2013, 12:58 pm

≫ Next: How to change BJT area in PSPICE lite 16.6

≪ Previous: noisefile in a vdc source modeled by Verilog-A

Good afternoon,

Under the Design Parameter Editor / Edit global dynamic shape parameters / Thermal reilef connects, I select the button for 'Use thermal width oversize of:' and set it to "0" so that my thermial reliefs will use the width I enter in the constraint manager. However, after I select the OK buttons and reopen the window the 'Use fixed thermal width of:' button is selected. I am guessing there is a setting I must have set, but can not find it.

Thank you for any help,

↧

How to change BJT area in PSPICE lite 16.6

September 27, 2013, 2:01 pm

≫ Next: CtoS fails when 'allocate_registers' command used

≪ Previous: Global relief settings

Hello,

I'm a student working on a project, and I need to know how to change the area of BJTs in my ORCAD simulation (16.6 lite)

I've looked at multiple google sites, but none of the info I can find is applicable. My professor is unable to help, since his information comes from an outdated form of orcad.

I need to know how to

a. Change the area of an individual BJT

b. Not affect other BJTs of the same model.

Detailed help would be greatly appreciated!

↧