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Problem in Running UltrasimVerilog

May 20, 2013, 1:18 am
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Hi,

I have a circuit with all custom deisgned module, and a verilog functional module for generting the input stimulus for my custom designed block. When I try to simulate using UltrasimVerilog as my simulator [Ultrasim/Spectre when I run AMS by setting ADE(L) --> Setup --> Simulator/Directory/Host; Simulator to UltrasimVerilog]  there is a error message,

" Error found by UltraSim.

    Error(USIM-12701): The UltraSim-Verimix(mixed mode) simulator option is not compatible with 64-bit platforms. The UltraSim will exit the current session.Either run the simulation on a 32-bit platform or turn off the UltraSim-Verimix Option before running the simulation again" 

I did go to ADE(L) --> Setup --> Environment, unchecked run with 64bit binaries. But still getting the same error.  

I am newbie to mixed signal simulations, I have used AMS as my simualtor before, but this is the first time I am trying with UltrasimVerilog.  

Can anyone enlighten me on the error and what to do?

And also I wish to know how to choose between Ultrasim/Spectre when I run AMS by setting ADE(L) --> Setup --> Simulator/Directory/Host; Simulator to AMS

Thanks!

Aarthy  

 

 

 

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Refdes Attribute ?

May 20, 2013, 1:22 am
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 Hi !

I want to get some atrtibute of refdes, such as rotation, xy, textBlock , isMirrored ( ex: refdes-> rotation), but i don't find any  function to do that. there is only  Text Attribute. How can i do it? Please help me?

Tks.

Luan.

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Problem in Running UltrasimVerilog

May 20, 2013, 1:23 am
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Hi,

I have a circuit with all custom deisgned module, and a verilog functional module for generting the input stimulus for my custom designed block. When I try to simulate using UltrasimVerilog as my simulator [Ultrasim/Spectre when I run AMS by setting ADE(L) --> Setup --> Simulator/Directory/Host; Simulator to UltrasimVerilog]  there is a error message,

" Error found by UltraSim.

   Error(USIM-12701): The UltraSim-Verimix(mixed mode) simulator option is not compatible with 64-bit platforms. The UltraSim will exit the current session.Either run the simulation on a 32-bit platform or turn off the UltraSim-Verimix Option before running the simulation again" 

I did go to ADE(L) --> Setup --> Environment, unchecked run with 64bit binaries. But still getting the same error.  

I am newbie to mixed signal simulations, I have used AMS as my simualtor before, but this is the first time I am trying with UltrasimVerilog.  

Can anyone enlighten me on the error and what to do?

And also I wish to know how to choose between Ultrasim/Spectre when I run AMS by setting ADE(L) --> Setup --> Simulator/Directory/Host; Simulator to AMS

Thanks!

Aarthy  
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Fillets in Allegro PCB Design L

May 16, 2013, 6:08 am
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Hello,

Can any one tell me how to put the Fillet, teardrop in  Allegro PCB Design L (legacy).

I saw some tutorial but under Gloss i can not see any options for the fillets.

How to do it????? 

thank you, 

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How to change component class (OrCAD Signal Explorer)

May 17, 2013, 3:00 am
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Hi

I'd like to change component class in PCB Editor (16.2) with OrCAD Signal Explorer before extracting xnets.

The only way I could do it was to change the refdes and use setup advisor->device setup.

Is there an easier way to do this with this tier?

Thanks

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PCB Ascii file

May 19, 2013, 10:52 pm
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Hi,

We are into manufacturing of PCB's and for one of the PCBs manufactured we want to perform flying probe test and for this we need a PCB ascii input file for the Seica FPT.

We have a .brd file for the board we have manufactured . How do i get a PCB ascii file for the .brd file with us.

Regards,

Madhuri 

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About the viewing of the information of the nodal voltage between schematic and Layout Editor

May 20, 2013, 7:57 pm
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Hi, everyone

What I used: Cadence IC51.41.151 /// Spectre 10.1.1.412.isr23 

After running the Spectre to extract the nodal voltage, Can we print this information

to the Layout XL(Layout Editor) on the polygon(Such as metal1/metal2/via etc.)?

 

This information already printed on the Cadence Schmatic view.

But as the circuit is huge, it's difficult to trace back the nodal voltage on the specific metal line in Layout Editor .

Can we acheive that?

thanks 

 

 

 

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Reading a parametrized cdf parameter

May 20, 2013, 10:19 am
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Hi, 

I am trying to read the CDF parameters of a FET.

My problem is that some of them refer to other CDF parameters via iPar().

So if I do: p1=cdfGetInstCDF(inst)~>parameters

v1=car(parameters)~>value 

Then I get v1="iPar("\width\")", instead of the numerical value.

This is fair enough and expected, but I was wondering if there is an easy way to get the evaluated value of the parameter returned rather than the string?

I could write a function to do this iterating through the parameters, but I am currently extracting the values of several parameters via lists (setof) and so if there is a built-in function to do this it would be more convenient. 

 

Thanks for the help.

Kostas 

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Check Parallel lines if intersect

May 21, 2013, 8:28 am
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Image and video hosting by TinyPic

given image above,

I would like to check both segments (maroon/orange line could be in any slope value) which are parallel to each other if they intersect.

dashed lines are the perpendicular lines of the maroon or of the orange line (my plan is to use these to get the intersections) .

The problem now is, how can i get the points of the perpendicular lines.

Im welcome for other suggestions.

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MIL-STD-1553 trace routing

April 2, 2013, 5:34 am
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A lot of boards I have done over the years have used MIL-STD-1553 communications. Normally these were boards where the coupling transformers were located close to the connector. The manufacturer of the coupling xfmrs and transceiver recommends not having any power or ground planes directly under the 1553 traces. For previous designs this was not an issue. I am now working on a design where I have to route the 1553 through several boards before it gets to the outside world connector.

In order to not have voids through the planes, I am planning on routing the 1553 traces down the outer edges of the boards. I was just curious if there are nay designers out there that have 1553 experience and what their thoughts on this may be.

I have contacted the Applications Engineer for the pars we are using but he only refers me to the data sheet which is somewhat vague.

Tom

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Modify film_reorder.il

May 21, 2013, 10:18 am
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I have been looking at the program "film_reorder.il" (available at cadence.com) and have found it useful but would like to make a small modification to it.  After you have selected a layer to be moved (up or down) in the list you have to re-select it if you want to move it more than one position.  Does anyone know of a way to modify this program so the selected layer stays selected until another layer is selected?  I would like to just click the up/down arrow X times until it is moved into the correct position without having to keep re-selecting the layer.

Thanks!

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umc180nm symmetric inductor

May 21, 2013, 10:33 pm
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iam using cadence with umc 180nm foundary file,where can i find the symmetric inductor in your tool.

how to get  quality factor  for symmetric inductor

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how to reduce explored

May 21, 2013, 10:36 pm
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Hi,

 

Iam using IFV for formal property checking and i have some of the assertions/Property explored.How to make them either pass/fail.

 

Thanks

Bharath 

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AMS Designer & Parameter Arrays

May 21, 2013, 5:38 am
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Hello everybody,

I would like to run a mixed mode simulation using some VerilogAMS code. In this code I currently use some parameter arrays to hand over parameters. Unfortunately I get the message that parameter arrays are not supported during the netlisting.

The simpliest solution would be to split up the parameter arrays, but I do not want to do this.

Has anybody an idea how I might overcome this problem without rewritting all of the code?

Thank you very much,
Markus

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ASCII waveform file format for Virtuoso Visualization and Analysis XL?

May 14, 2013, 8:35 am
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I have some waveforms captured from a high speed scope that I'd like to display alongside spectre simulation results in "Virtuoso Visualization and Analysis XL" viewer using ADE-XL.  I'd assumed it would support some form of ASCII format such as ASCII tr0 but the Cadence docs dont list any ASCII file formats in the table of supported waveform data files.  I cant see any way of getting into sst2 or psf formats from ASCII either.  Does anyone have any ideas on how I might do this?

AndyS

 

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problem: W and L of a transistor not shown in edit-> object-> properties

May 22, 2013, 10:32 am
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When editing a transistor in schematic editor L (version 615), the width (w) and length (l) are not shown in the form so that they can not be changed. The CDF parameters shown are M gates per device, maskLayoutViewName, parasitic calculation.

 Then from CIW -> tools ->CDF->edit..., it is found that, for that transistor, in the "Display Condition" column, for width,  XfabFormIsInToolDisplay (w) and for length, XfabFormIsInToolDisplay (l). I tried to delete them but did not solve the problem.

 Xfab is the technology. 

Anyone knows the issue?

Thanks! 

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Power Stripe - Power Via Generation in Encounter

May 22, 2013, 3:05 pm
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I am trying to use a power ring, special routing, and power stripes for my power routing. I can set up the ring, special routing, and stripes correctly as far as location is concerned. However, I am having spacing violations in Encounter (and after exporting to Cadence using oaout) where it places power vias from the top metal down to the special routing during the power stripe insertion. My power rails are max-sized in the cells based on our cell template, but it adds extra metal around the vias, causing these spacing issues.

It seems to be generating the power vias without checking information in the tech LEF. It seems to be disregarding my VIARULE GENERATE DEFAULT statements.

Is there a specific location I can set the power via rules so that the enclosure of metal 1 is smaller? 

 

Thanks,

Brett Sparkman 

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How often does AMS flush outputs by default during a simulation?

May 22, 2013, 4:46 pm
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Iam running a long transient simulation using AMS designer. I would like to flush the simulation results periodically in order to view results as the simulation progresses.

Do we have flushpoints and flushtime(s) options available in AMS just as we have in spectre? Please suggest me.I am using INCSIV 12.2 version.

Thank you in Advance.


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ERROR (VACOMP-1008): Cannot compile ahdlcmi module library when I practice the AMSKIT615 package.

May 22, 2013, 4:56 pm
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I got this error when I was practicing Cadence AMS Methodology kit (05B_AnalogBlockDesignOptimization) using IC6.1.5. My OS is Unix 32-bit.

"ERROR (ADEXL-5011): While simulating run LocalOpt.1, point 48, test freq_low, received error:

Simulation Error:

------------------------------

Simulator failed to complete the simulation.

 Error found by spectre during AHDL read-in.

Error found by spectre during AHDL read-in.

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/5084_dfII_zambezi_pll_vco_thermdecode_veriloga_veriloga

.va.pll_vco_thermdecode.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. 

If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model f

iles, and any other information that can help identify the problem.

ERROR (SFE-91): Error when elaborating the instance pll_vco_thermdecode. Simulation should be terminated.

Error found by spectre during AHDL read-in.

Error found by spectre during AHDL read-in.

ERROR (VACOMP-2235): Internal Compiling Error: The built-in termcurs parameter is redefined in module 'pll_vco_thermdecode'.

ERROR (VACOMP-1816): Exiting AHDL compilation.

ERROR (SFE-91): Error when elaborating the instance pll_vco_thermdecode. Simulation should be terminated.

Error found by spectre during AHDL read-in.

Error found by spectre during AHDL read-in.

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/5084_dfII_zambezi_sim_pll_vco_stim_veriloga_veriloga.va

.pll_vco_stim.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the rea

son for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and 

any other information that can help identify the problem.

ERROR (SFE-91): Error when elaborating the instance pll_vco_stim. Simulation should be terminated.

 For details open log: /users/labnet2/fs5/tl4528/my_AMS/AMSKIT_tl4528/modules/05_AMSConstraintDrivenBlockCreate/05B_AnalogBlockDesignOptimization/DB/simulation/AMSBC/pll_vco_sim/adexl_opt/results/data/LocalOpt.1/48/freq_low/psf/spectre.out

 ------------------------------

For more details, consult the job log file:

/users/labnet2/fs5/tl4528/my_AMS/AMSKIT_tl4528/modules/05_AMSConstraintDrivenBlockCreate/05B_AnalogBlockDesignOptimization/DB/logs_tl4528/Job0.log" 

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

This is just a section of error message. Other message are all similar like this section. 

Also this message in CIW happened when I tried to run any simulation or optimaizaiton followed by AMSKit 05B tutorial. 

If someone could help me, I would appreiciate that.

Thanks. 

 

 

 

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Sanity Check how do I Compare netlist from capture and Allegro.

May 22, 2013, 8:04 am
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In other PCB/SCH tools I have used it was possible to generate a netlist from both the schematic and then from the completed board so as to verify the actual board did indeed match the schematic.

Basically it is just a netlist compare utility. Kind of handy during post processing before you send a board out to be made.

Was wondering if it is possible to do this with capture/allegro and if a utility exists to do this ?

Thanks Scott

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